[coreboot-gerrit] Change in coreboot[master]: mb/google/fizz: Enable I2C bus 2
Zhongze Hu (Code Review)
gerrit at coreboot.org
Sat Mar 17 00:48:33 CET 2018
Zhongze Hu has uploaded this change for review. ( https://review.coreboot.org/25257
Change subject: mb/google/fizz: Enable I2C bus 2
......................................................................
mb/google/fizz: Enable I2C bus 2
I2C bus 2 goes to the custom add-in card slot and it was disalbed cuase
it was idle.
Google CFM add-in card is going to use this I2C bus so it needs to be
re-enabled.
BUG=b:73006317
TEST=Tested with add-in card on fizz hardware and verified I2C bus 2 is
working properly.
BRANCH=fizz
Change-Id: Id5981a6cfc77cdeaea04dc505d77ca94eef98c37
---
M 3rdparty/blobs
M 3rdparty/chromeec
M src/mainboard/google/fizz/devicetree.cb
3 files changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/25257/1
diff --git a/3rdparty/blobs b/3rdparty/blobs
index a4b5613..19dea8d 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit a4b561391f59e09059ce851fa19b64ca945672d5
+Subproject commit 19dea8d171544f01f12ee6b78af0cc356ab994aa
diff --git a/3rdparty/chromeec b/3rdparty/chromeec
index 927b64a..9fb1038 160000
--- a/3rdparty/chromeec
+++ b/3rdparty/chromeec
@@ -1 +1 @@
-Subproject commit 927b64a0ba8f6362daf2e9a6c7eabf23815ae95a
+Subproject commit 9fb10386a720d270e37ce61da3ff3a6d5a69951e
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index e7654cf..2b87e31 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -296,9 +296,9 @@
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
- [PchSerialIoIndexI2C0] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
- [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
@@ -329,9 +329,9 @@
device pci 14.0 on end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
- device pci 15.0 off end # I2C #0
+ device pci 15.0 on end # I2C #0
device pci 15.1 off end # I2C #1
- device pci 15.2 off end # I2C #2
+ device pci 15.2 on end # I2C #2
device pci 15.3 off end # I2C #3
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id5981a6cfc77cdeaea04dc505d77ca94eef98c37
Gerrit-Change-Number: 25257
Gerrit-PatchSet: 1
Gerrit-Owner: Zhongze Hu <frankhu at chromium.org>
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