[coreboot-gerrit] Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Enable SATA in device tree

[Kin Wai Ng (Code Review)]

Hello Naresh Solanki, Subrata Banik, Balaji Manigandan, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi,

I'd like you to do a code review. Please visit

    https://review.coreboot.org/25237

to review the following change.


Change subject: mainboard/intel/coffeelake_rvp: Enable SATA in device tree
......................................................................

mainboard/intel/coffeelake_rvp: Enable SATA in device tree

Change-Id: Icac1e66f44a1000b5e12770e5978aada5c9a0a32
Signed-off-by: Ng Kin Wai <kin.wai.ng at intel.com>
---
M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
1 file changed, 12 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/25237/1

diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
index 1b779d9..f84400d 100755
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
@@ -31,6 +31,17 @@
 	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
 	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
 
+	register "SataEnable" = "1"
+	register "SataSalpSupport" = "1"
+	register "SataPortsEnable[0]" = "1"
+	register "SataPortsEnable[1]" = "1"
+	register "SataPortsEnable[2]" = "1"
+	register "SataPortsEnable[3]" = "1"
+	register "SataPortsEnable[4]" = "1"
+	register "SataPortsEnable[5]" = "1"
+	register "SataPortsEnable[6]" = "1"
+	register "SataPortsEnable[7]" = "1"
+
 	register "PchHdaDspEnable" = "1"
 	register "PchHdaAudioLinkHda" = "1"
 
@@ -121,7 +132,7 @@
 		device pci 16.3 off end # Management Engine KT Redirection
 		device pci 16.4 off end # Management Engine Interface 3
 		device pci 16.5 off end # Management Engine Interface 4
-		device pci 17.0 off  end # SATA
+		device pci 17.0 on  end # SATA
 		device pci 19.0 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
 		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Icac1e66f44a1000b5e12770e5978aada5c9a0a32
Gerrit-Change-Number: 25237
Gerrit-PatchSet: 1
Gerrit-Owner: Kin Wai Ng <kin.wai.ng at intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela at intel.com>
Gerrit-Reviewer: Naresh Solanki <naresh.solanki at intel.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
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