[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Save/restore GMA OpRegion address

Matt DeVillier (Code Review) gerrit at coreboot.org
Thu Mar 15 18:09:30 CET 2018 

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/25198


Change subject: soc/intel/skylake: Save/restore GMA OpRegion address
......................................................................

soc/intel/skylake: Save/restore GMA OpRegion address

Add global/ACPI nvs variables required for IGD OpRegion.
Add functions necessary to save the ACPI OpRegion table
address in ASLB, and restore table address upon S3 resume.

Implementation modeled on existing Baytrail code.

Test: boot Windows 10 on google/chell with Tianocore payload and
GOP display init, observe display driver loaded and functional,
display not black screen when resuming from S3 suspend.

Change-Id: Icd6b514e531eec6e49dbb03eb765144f41c1e31b
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/soc/intel/skylake/acpi/globalnvs.asl
M src/soc/intel/skylake/graphics.c
M src/soc/intel/skylake/include/soc/nvs.h
3 files changed, 98 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/25198/1

diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index 5564f02..c4544e8 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -71,6 +71,48 @@
 	EMNA,	64,	// 0x44 - 0x4B EPC base address
 	ELNG,	64,	// 0x4C - 0x53 EPC Length
 
+	/* IGD OpRegion */
+	Offset (0xb4),
+	ASLB,	32,	// 0xb4 - IGD OpRegion Base Address
+	IBTT,	 8,	// 0xb8 - IGD boot panel device
+	IPAT,	 8,	// 0xb9 - IGD panel type cmos option
+	ITVF,	 8,	// 0xba - IGD TV format cmos option
+	ITVM,	 8,	// 0xbb - IGD TV minor format option
+	IPSC,	 8,	// 0xbc - IGD panel scaling
+	IBLC,	 8,	// 0xbd - IGD BLC config
+	IBIA,	 8,	// 0xbe - IGD BIA config
+	ISSC,	 8,	// 0xbf - IGD SSC config
+	I409,	 8,	// 0xc0 - IGD 0409 modified settings
+	I509,	 8,	// 0xc1 - IGD 0509 modified settings
+	I609,	 8,	// 0xc2 - IGD 0609 modified settings
+	I709,	 8,	// 0xc3 - IGD 0709 modified settings
+	IDMM,	 8,	// 0xc4 - IGD Power conservation feature
+	IDMS,	 8,	// 0xc5 - IGD DVMT memory size
+	IF1E,	 8,	// 0xc6 - IGD function 1 enable
+	HVCO,	 8,	// 0xc7 - IGD HPLL VCO
+	NXD1,	32,	// 0xc8 - IGD _DGS next DID1
+	NXD2,	32,	// 0xcc - IGD _DGS next DID2
+	NXD3,	32,	// 0xd0 - IGD _DGS next DID3
+	NXD4,	32,	// 0xd4 - IGD _DGS next DID4
+	NXD5,	32,	// 0xd8 - IGD _DGS next DID5
+	NXD6,	32,	// 0xdc - IGD _DGS next DID6
+	NXD7,	32,	// 0xe0 - IGD _DGS next DID7
+	NXD8,	32,	// 0xe4 - IGD _DGS next DID8
+
+	ISCI,	 8,	// 0xe8 - IGD SMI/SCI mode (0: SCI)
+	PAVP,	 8,	// 0xe9 - IGD PAVP data
+	Offset (0xeb),
+	OSCC,	 8,	// 0xeb - PCIe OSC control
+	NPCE,	 8,	// 0xec - native pcie support
+	PLFL,	 8,	// 0xed - platform flavor
+	BREV,	 8,	// 0xee - board revision
+	DPBM,	 8,	// 0xef - digital port b mode
+	DPCM,	 8,	// 0xf0 - digital port c mode
+	DPDM,	 8,	// 0xf1 - digital port d mode
+	ALFP,	 8,	// 0xf2 - active lfp
+	IMON,	 8,	// 0xf3 - current graphics turbo imon value
+	MMIO,	 8,	// 0xf4 - 64bit mmio support
+
 	/* ChromeOS specific */
 	Offset (0x100),
 	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c
index 95a37d6..bda08c5 100644
--- a/src/soc/intel/skylake/graphics.c
+++ b/src/soc/intel/skylake/graphics.c
@@ -14,11 +14,13 @@
  * GNU General Public License for more details.
  */
 
+#include <cbmem.h>
 #include <console/console.h>
 #include <device/pci.h>
 #include <drivers/intel/gma/i915_reg.h>
 #include <intelblocks/graphics.h>
 #include <drivers/intel/gma/opregion.h>
+#include <soc/nvs.h>
 #include <soc/ramstage.h>
 
 uintptr_t fsp_soc_get_igd_bar(void)
@@ -60,6 +62,21 @@
 
 	/* Initialize PCI device, load/execute BIOS Option ROM */
 	pci_dev_init(dev);
+
+	intel_gma_restore_opregion();
+}
+
+uintptr_t gma_get_gnvs_aslb(const void *gnvs)
+{
+	const global_nvs_t *gnvs_ptr = gnvs;
+	return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
+}
+
+void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
+{
+	global_nvs_t *gnvs_ptr = gnvs;
+	if (gnvs_ptr)
+		gnvs_ptr->aslb = aslb;
 }
 
 /* Initialize IGD OpRegion, called from ACPI code */
@@ -72,6 +89,7 @@
 		uintptr_t current, struct acpi_rsdp *rsdp)
 {
 	igd_opregion_t *opregion;
+	global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
 
 	/* If GOP is not used, exit here */
 	if (!IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE))
@@ -86,7 +104,8 @@
 
 	if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
 		return current;
-
+	if (gnvs)
+		gnvs->aslb = (u32)(uintptr_t)opregion;
 	update_igd_opregion(opregion);
 	current += sizeof(igd_opregion_t);
 	current = acpi_align_current(current);
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index 8bc4d8d..bd3610e 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -62,7 +62,42 @@
 	u8	ecps; /* 0x43 - SGX Enabled status */
 	u64	emna; /* 0x44 - 0x4B EPC base address */
 	u64	elng; /* 0x4C - 0x53 EPC Length */
-	u8	unused[172];
+	u8	rsvd[96];
+
+	/* IGD OpRegion */
+	u32	aslb; /* 0xb4 - IGD OpRegion Base Address */
+	u8	ibtt; /* 0xb8 - IGD boot type */
+	u8	ipat; /* 0xb9 - IGD panel type */
+	u8	itvf; /* 0xba - IGD TV format */
+	u8	itvm; /* 0xbb - IGD TV minor format */
+	u8	ipsc; /* 0xbc - IGD Panel Scaling */
+	u8	iblc; /* 0xbd - IGD BLC configuration */
+	u8	ibia; /* 0xbe - IGD BIA configuration */
+	u8	issc; /* 0xbf - IGD SSC configuration */
+	u8	i409; /* 0xc0 - IGD 0409 modified settings */
+	u8	i509; /* 0xc1 - IGD 0509 modified settings */
+	u8	i609; /* 0xc2 - IGD 0609 modified settings */
+	u8	i709; /* 0xc3 - IGD 0709 modified settings */
+	u8	idmm; /* 0xc4 - IGD Power Conservation */
+	u8	idms; /* 0xc5 - IGD DVMT memory size */
+	u8	if1e; /* 0xc6 - IGD Function 1 Enable */
+	u8	hvco; /* 0xc7 - IGD HPLL VCO */
+	u32	nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
+	u8	isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
+	u8	pavp; /* 0xe9 - IGD PAVP data */
+	u8	rsvd12; /* 0xea - rsvd */
+	u8	oscc; /* 0xeb - PCIe OSC control */
+	u8	npce; /* 0xec - native pcie support */
+	u8	plfl; /* 0xed - platform flavor */
+	u8	brev; /* 0xee - board revision */
+	u8	dpbm; /* 0xef - digital port b mode */
+	u8	dpcm; /* 0xf0 - digital port c mode */
+	u8	dpdm; /* 0xf1 - digital port c mode */
+	u8	alfp; /* 0xf2 - active lfp */
+	u8	imon; /* 0xf3 - current graphics turbo imon value */
+	u8	mmio; /* 0xf4 - 64bit mmio support */
+
+	u8	unused[11];
 
 	/* ChromeOS specific (0x100 - 0xfff) */
 	chromeos_acpi_t chromeos;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Icd6b514e531eec6e49dbb03eb765144f41c1e31b
Gerrit-Change-Number: 25198
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
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