[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/25186 )

Change subject: soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array
......................................................................

soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array

This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ#
from mainboards instead of defining a separate property for each root
port. This allows us to use memcpy to copy the entire array into FSP
params as well as new properties for PCIe root ports can be added as
arrays in future CLs.

BUG=b:74633273
BRANCH=reef,coral

Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7
Signed-off-by: Furquan Shaikh <furquan at google.com>
---
M src/mainboard/google/reef/variants/baseboard/devicetree.cb
M src/mainboard/google/reef/variants/coral/devicetree.cb
M src/mainboard/google/reef/variants/pyro/devicetree.cb
M src/mainboard/google/reef/variants/sand/devicetree.cb
M src/mainboard/google/reef/variants/snappy/devicetree.cb
M src/mainboard/intel/apollolake_rvp/devicetree.cb
M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
M src/mainboard/intel/leafhill/devicetree.cb
M src/mainboard/intel/minnow3/devicetree.cb
M src/mainboard/siemens/mc_apl1/devicetree.cb
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/chip.h
12 files changed, 64 insertions(+), 72 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/25186/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7
Gerrit-Change-Number: 25186
Gerrit-PatchSet: 2
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
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