[coreboot-gerrit] Change in coreboot[master]: soc/intel/braswell: add ACPI for eMMC/SD devices in PCI mode

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/24988


Change subject: soc/intel/braswell: add ACPI for eMMC/SD devices in PCI mode
......................................................................

soc/intel/braswell: add ACPI for eMMC/SD devices in PCI mode

Allows eMMC in PCI mode to be seen/used by Windows.

Test: boot Windows installer on google/edgar, observe internal
eMMC storage available for installation when eMMC in PCI (vs ACPI) mode.

Change-Id: I4272c198e5e675f451a1f4de5d46e3cd96371446
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/soc/intel/braswell/acpi/scc.asl
1 file changed, 38 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/24988/1

diff --git a/src/soc/intel/braswell/acpi/scc.asl b/src/soc/intel/braswell/acpi/scc.asl
index 95f2244..128edc5 100644
--- a/src/soc/intel/braswell/acpi/scc.asl
+++ b/src/soc/intel/braswell/acpi/scc.asl
@@ -77,6 +77,44 @@
 	}
 }
 
+Device (PEMC)
+{
+	Name (_ADR, 0x00100000)  // _ADR: Address
+
+	OperationRegion (SDIO, PCI_Config, 0x84, 0x04)
+	Field (SDIO, WordAcc, NoLock, Preserve)
+	{
+		Offset (0x01),
+		PMEE, 1,
+		, 6,
+		PMES, 1
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		If (LEqual (\C0EN, 1)) {
+			Return (0x0)
+		}
+		Else
+		{
+			Return (0xF)
+		}
+	}
+
+	Method (_DSW, 3, NotSerialized)
+	{
+	}
+
+	Device (CARD)
+	{
+		Name (_ADR, 0x08)
+		Method (_RMV, 0, NotSerialized)
+		{
+			Return (Zero)
+		}
+	}
+}
+
 Device (SDIO)
 {
 	Name (_HID, "INT33BB")

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4272c198e5e675f451a1f4de5d46e3cd96371446
Gerrit-Change-Number: 24988
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
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