[coreboot-gerrit] Change in coreboot[master]: nocturne: Do not set 4 LSB of CRTL0

[Gwendal Grignou (Code Review)]

Gwendal Grignou has uploaded this change for review. ( https://review.coreboot.org/27265


Change subject: nocturne: Do not set 4 LSB of CRTL0
......................................................................

nocturne: Do not set 4 LSB of CRTL0

These bits start the acquisition process. They should only be set by the
driver.

BUG=b:74363445
TEST=compile

Change-Id: I9e10f5570ac82124f7f4b5cc7aaad27da0c578be
Signed-off-by: Gwendal Grignou <gwendal at chromium.org>
---
M 3rdparty/arm-trusted-firmware
M 3rdparty/blobs
M 3rdparty/chromeec
M 3rdparty/libgfxinit
M 3rdparty/libhwbase
M 3rdparty/vboot
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
M util/nvidia/cbootimage
8 files changed, 9 insertions(+), 9 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/27265/1

diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware
index 693e278..236c27d 160000
--- a/3rdparty/arm-trusted-firmware
+++ b/3rdparty/arm-trusted-firmware
@@ -1 +1 @@
-Subproject commit 693e278e308441d716f7f5116c43aa150955da31
+Subproject commit 236c27d21f52ad8f0a998e54774e3d8a4b59129d
diff --git a/3rdparty/blobs b/3rdparty/blobs
index 78a02a7..8e9f99b 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit 78a02a7f9d979fcc864638cc40084e662476095f
+Subproject commit 8e9f99b3e60d0ffe8b67cc93ea4ab1b9ed191e45
diff --git a/3rdparty/chromeec b/3rdparty/chromeec
index 11bd4c0..bcffec7 160000
--- a/3rdparty/chromeec
+++ b/3rdparty/chromeec
@@ -1 +1 @@
-Subproject commit 11bd4c0f4d11357ab830982d7dec164813c886dd
+Subproject commit bcffec7fdc50e959cb298d094d8af472777dba75
diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit
index 718c79b..88a7f17 160000
--- a/3rdparty/libgfxinit
+++ b/3rdparty/libgfxinit
@@ -1 +1 @@
-Subproject commit 718c79bb0713b5b90c9cc44e03197dc777066e3d
+Subproject commit 88a7f17b7d7a4f8a4d25ef6b87c71236b0862f5d
diff --git a/3rdparty/libhwbase b/3rdparty/libhwbase
index 637f2a4..aab715f 160000
--- a/3rdparty/libhwbase
+++ b/3rdparty/libhwbase
@@ -1 +1 @@
-Subproject commit 637f2a4f21ead8ccc45d5256834eb27ce72088db
+Subproject commit aab715f166bf1b54cfbd6982e8df49248ea544d8
diff --git a/3rdparty/vboot b/3rdparty/vboot
index 392211f..adfafba 160000
--- a/3rdparty/vboot
+++ b/3rdparty/vboot
@@ -1 +1 @@
-Subproject commit 392211f0358919d510179ad399d8f056180e652e
+Subproject commit adfafba793684ed92965dfbd86b3fb3463975d8c
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 09b7ef9..17bd3c0 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -305,7 +305,7 @@
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)"
 				register "speed" = "I2C_SPEED_FAST_PLUS"
 				register "uid" = "0"
-				register "reg_prox_ctrl0" = "0x1a"
+				register "reg_prox_ctrl0" = "0x10"
 				register "reg_prox_ctrl1" = "0x00"
 				register "reg_prox_ctrl2" = "0x84"
 				register "reg_prox_ctrl3" = "0x0e"
@@ -346,7 +346,7 @@
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D10_IRQ)"
 				register "speed" = "I2C_SPEED_FAST_PLUS"
 				register "uid" = "1"
-				register "reg_prox_ctrl0" = "0x1a"
+				register "reg_prox_ctrl0" = "0x10"
 				register "reg_prox_ctrl1" = "0x00"
 				register "reg_prox_ctrl2" = "0x84"
 				register "reg_prox_ctrl3" = "0x0e"
diff --git a/util/nvidia/cbootimage b/util/nvidia/cbootimage
index 64045f9..efe19b2 160000
--- a/util/nvidia/cbootimage
+++ b/util/nvidia/cbootimage
@@ -1 +1 @@
-Subproject commit 64045f993c2cd8989838aeaad3d22107d96d5596
+Subproject commit efe19b2eb9db7bb3ba913f0af7d5ececb173fe82

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9e10f5570ac82124f7f4b5cc7aaad27da0c578be
Gerrit-Change-Number: 27265
Gerrit-PatchSet: 1
Gerrit-Owner: Gwendal Grignou <gwendal at chromium.org>
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