[coreboot-gerrit] Change in coreboot[master]: nb/intel/x4x: Don't use PCI operations on the pci_domain device

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27245


Change subject: nb/intel/x4x: Don't use PCI operations on the pci_domain device
......................................................................

nb/intel/x4x: Don't use PCI operations on the pci_domain device

The pci_domain just happens to have bus, device and function set to 0,
which is why to code works.

This patch still keeps adding the fixed resources in the pci_domain
ops since moving it to the PCI ops which could properly use the
function argument for PCI operations would require all PCI IDs to be
added or else breakages are to be expected.

Change-Id: Iabfd15884ec8feb846d01b6af3c4afe5c1494feb
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/northbridge/intel/x4x/northbridge.c
1 file changed, 7 insertions(+), 5 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/27245/1

diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index 3e50229..08e5e1c 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -44,16 +44,18 @@
 
 	pci_domain_read_resources(dev);
 
+	struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0));
+
 	/* Top of Upper Usable DRAM, including remap */
-	touud = pci_read_config16(dev, D0F0_TOUUD);
+	touud = pci_read_config16(mch, D0F0_TOUUD);
 	touud <<= 20;
 
 	/* Top of Lower Usable DRAM */
-	tolud = pci_read_config16(dev, D0F0_TOLUD) & 0xfff0;
+	tolud = pci_read_config16(mch, D0F0_TOLUD) & 0xfff0;
 	tolud <<= 16;
 
 	/* Top of Memory - does not account for any UMA */
-	tom = pci_read_config16(dev, D0F0_TOM) & 0x01ff;
+	tom = pci_read_config16(mch, D0F0_TOM) & 0x01ff;
 	tom <<= 26;
 
 	printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n",
@@ -63,7 +65,7 @@
 
 	/* Graphics memory comes next */
 
-	const u16 ggc = pci_read_config16(dev, D0F0_GGC);
+	const u16 ggc = pci_read_config16(mch, D0F0_GGC);
 	printk(BIOS_DEBUG, "IGD decoded, subtracting ");
 
 	/* Graphics memory */
@@ -79,7 +81,7 @@
 	uma_sizek += gsm_sizek;
 
 	printk(BIOS_DEBUG, "TSEG decoded, subtracting ");
-	reg8 = pci_read_config8(dev, D0F0_ESMRAMC);
+	reg8 = pci_read_config8(mch, D0F0_ESMRAMC);
 	reg8 >>= 1;
 	reg8 &= 3;
 	switch (reg8) {

-- 
To view, visit https://review.coreboot.org/27245
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iabfd15884ec8feb846d01b6af3c4afe5c1494feb
Gerrit-Change-Number: 27245
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180626/9f3e1882/attachment.html>