[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: unify definition for spi base address

Patrick Georgi (Code Review) gerrit at coreboot.org
Thu Jun 21 17:55:10 CEST 2018


Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27097 )

Change subject: soc/intel/apollolake: unify definition for spi base address
......................................................................

soc/intel/apollolake: unify definition for spi base address

Use SPI_BASE_ADDRESS instead of PRERAM_SPI_BASE_ADDRESS like
big core in order make common code implementation straightforward.

Change-Id: Ibcb013fc95de29234253e89c9ca100cc468d44f6
Signed-off-by: Bora Guvendik <bora.guvendik at intel.com>
Reviewed-on: https://review.coreboot.org/27097
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Furquan Shaikh <furquan at google.com>
---
M src/soc/intel/apollolake/bootblock/bootblock.c
M src/soc/intel/apollolake/include/soc/iomap.h
2 files changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved



diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index c7ababd..ead6bf3 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -106,7 +106,7 @@
 
 	enable_pm_timer_emulation();
 
-	fast_spi_early_init(PRERAM_SPI_BASE_ADDRESS);
+	fast_spi_early_init(SPI_BASE_ADDRESS);
 
 	fast_spi_cache_bios_region();
 
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index 9a2500c..479882f 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -47,7 +47,7 @@
 #define HECI1_BASE_ADDRESS		0xfed1a000
 
 /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */
-#define PRERAM_SPI_BASE_ADDRESS		0xfe010000
+#define SPI_BASE_ADDRESS		0xfe010000
 #define EARLY_GSPI_BASE_ADDRESS		0xfe011000
 
 /* Temporary BAR for early I2C bus access */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Ibcb013fc95de29234253e89c9ca100cc468d44f6
Gerrit-Change-Number: 27097
Gerrit-PatchSet: 2
Gerrit-Owner: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela at intel.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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