[coreboot-gerrit] Change in coreboot[master]: soc/intel/{skl, kbl}: ensure C1E is disabled after S3 resume

[Cole Nelson (Code Review)]

Cole Nelson has uploaded this change for review. ( https://review.coreboot.org/27125


Change subject: soc/intel/{skl,kbl}: ensure C1E is disabled after S3 resume
......................................................................

soc/intel/{skl,kbl}: ensure C1E is disabled after S3 resume

C1E is disabled by the kernel driver intel_idle at boot.  This does not
address the S3 resume case, so we lose state and C1E is enabled after S3
resume.

Disable C1E for GLK as it is for APL.  This gives a coherent state before
and after S3 resume.

TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3
resume with bit [1] set to zero (0x20005d).

Change-Id: I1343f343bfac9b787f13c15b812c0a201dcccb38
Signed-off-by: Cole Nelson <colex.nelson at intel.com>
---
M src/soc/intel/skylake/cpu.c
1 file changed, 1 insertion(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/27125/1

diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index d386d1f..3a499ce 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -310,9 +310,9 @@
 	msr.hi = 0;
 	wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
 
-	/* Enable PROCHOT */
 	msr = rdmsr(MSR_POWER_CTL);
 	msr.lo |= (1 << 0);	/* Enable Bi-directional PROCHOT as an input*/
+	msr.lo &= ~POWER_CTL_C1E_MASK;	/* Disable C1E */
 	msr.lo |= (1 << 23);	/* Lock it */
 	wrmsr(MSR_POWER_CTL, msr);
 }

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1343f343bfac9b787f13c15b812c0a201dcccb38
Gerrit-Change-Number: 27125
Gerrit-PatchSet: 1
Gerrit-Owner: Cole Nelson <colex.nelson at intel.com>
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