[coreboot-gerrit] Change in coreboot[master]: src: Use pci_devfn_t instead of device_t
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Wed Jun 13 08:42:01 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27085
Change subject: src: Use pci_devfn_t instead of device_t
......................................................................
src: Use pci_devfn_t instead of device_t
Change-Id: I0ab62dd90a5ffdb504f5b9951877a32c345fc44d
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/lib/debug.c
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/lpc/lpc_lib.c
M src/soc/intel/common/block/pcr/pcr.c
M src/soc/intel/common/block/uart/uart.c
8 files changed, 66 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/27085/1
diff --git a/src/lib/debug.c b/src/lib/debug.c
index 6ae5985..80ee416 100644
--- a/src/lib/debug.c
+++ b/src/lib/debug.c
@@ -22,7 +22,11 @@
static inline void print_pci_devices(void)
{
- device_t dev;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
for (dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0x00, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
u32 id;
@@ -56,7 +60,11 @@
static inline void dump_pci_devices(void)
{
- device_t dev;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
for (dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
u32 id;
diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c
index 02ab886..01a4928 100644
--- a/src/soc/intel/common/block/acpi/acpi.c
+++ b/src/soc/intel/common/block/acpi/acpi.c
@@ -164,7 +164,7 @@
soc_fill_fadt(fadt);
}
-unsigned long southbridge_write_acpi_tables(device_t device,
+unsigned long southbridge_write_acpi_tables(struct device *device,
unsigned long current,
struct acpi_rsdp *rsdp)
{
@@ -224,7 +224,7 @@
{
}
-void southbridge_inject_dsdt(device_t device)
+void southbridge_inject_dsdt(struct device *device)
{
struct global_nvs_t *gnvs;
@@ -407,7 +407,7 @@
{
}
-void generate_cpu_entries(device_t device)
+void generate_cpu_entries(struct device *device)
{
int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS;
int plen = 6;
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 97ad176..e264348 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -31,7 +31,7 @@
static const void *microcode_patch;
/* SoC override function */
-__weak void soc_core_init(device_t dev)
+__weak void soc_core_init(struct device *dev)
{
/* no-op */
}
@@ -41,7 +41,7 @@
/* no-op */
}
-static void init_one_cpu(device_t dev)
+static void init_one_cpu(struct device *dev)
{
soc_core_init(dev);
intel_microcode_load_unlocked(microcode_patch);
@@ -121,7 +121,7 @@
static void init_cpus(void *unused)
{
- device_t dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);
+ struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);
assert(dev != NULL);
microcode_patch = intel_microcode_find();
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 4991db6..8651297 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -80,7 +80,11 @@
void heci_init(uintptr_t tempbar)
{
struct cse_device *cse = car_get_var_ptr(&g_cse);
- device_t dev = PCH_DEV_CSE;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_CSE;
+#else
+ struct device *dev = PCH_DEV_CSE;
+#endif
u8 pcireg;
/* Assume it is already initialized, nothing else to do */
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index b13408a..e7f81fc 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -34,7 +34,11 @@
*/
void *fast_spi_get_bar(void)
{
- device_t dev = PCH_DEV_SPI;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_SPI;
+#else
+ struct device *dev = PCH_DEV_SPI;
+#endif
uintptr_t bar;
bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -51,7 +55,11 @@
*/
void fast_spi_init(void)
{
- device_t dev = PCH_DEV_SPI;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_SPI;
+#else
+ struct device *dev = PCH_DEV_SPI;
+#endif
uint8_t bios_cntl;
bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL);
@@ -71,7 +79,11 @@
*/
static void fast_spi_set_bios_control_reg(uint8_t bios_cntl_bit)
{
- device_t dev = PCH_DEV_SPI;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_SPI;
+#else
+ struct device *dev = PCH_DEV_SPI;
+#endif
uint8_t bc_cntl;
assert((bios_cntl_bit & (bios_cntl_bit - 1)) == 0);
@@ -253,7 +265,11 @@
*/
void fast_spi_early_init(uintptr_t spi_base_address)
{
- device_t dev = PCH_DEV_SPI;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_SPI;
+#else
+ struct device *dev = PCH_DEV_SPI;
+#endif
uint8_t pcireg;
/* Assign Resources to SPI Controller */
@@ -285,7 +301,11 @@
/* Enable SPI Write Protect. */
void fast_spi_enable_wp(void)
{
- device_t dev = PCH_DEV_SPI;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_SPI;
+#else
+ struct device *dev = PCH_DEV_SPI;
+#endif
uint8_t bios_cntl;
bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL);
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index 58b588e..d27f877 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -167,7 +167,11 @@
*/
static void lpc_set_bios_control_reg(uint8_t bios_cntl_bit)
{
- device_t dev = PCH_DEV_LPC;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_LPC;
+#else
+ struct device *dev = PCH_DEV_LPC;
+#endif
uint8_t bc_cntl;
assert(IS_POWER_OF_2(bios_cntl_bit));
@@ -210,7 +214,11 @@
*/
void lpc_set_serirq_mode(enum serirq_mode mode)
{
- device_t dev = PCH_DEV_LPC;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_LPC;
+#else
+ struct device *dev = PCH_DEV_LPC;
+#endif
uint8_t scnt;
scnt = pci_read_config8(dev, LPC_SERIRQ_CTL);
diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c
index cf50fdc..b8d798f 100644
--- a/src/soc/intel/common/block/pcr/pcr.c
+++ b/src/soc/intel/common/block/pcr/pcr.c
@@ -254,7 +254,11 @@
int pcr_execute_sideband_msg(struct pcr_sbi_msg *msg, uint32_t *data,
uint8_t *response)
{
- device_t dev = PCH_DEV_P2SB;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_P2SB;
+#else
+ struct device *dev = PCH_DEV_P2SB;
+#endif
uint32_t sbi_data;
uint16_t sbi_status;
uint16_t sbi_rid;
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index cdbe56b..b84a7ec 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -59,7 +59,11 @@
bool uart_debug_controller_is_initialized(void)
{
- device_t dev;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
uintptr_t base;
dev = pch_uart_get_debug_controller();
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0ab62dd90a5ffdb504f5b9951877a32c345fc44d
Gerrit-Change-Number: 27085
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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