[coreboot-gerrit] Change in coreboot[master]: sb/intel/lynxpoint: Get rid of device_t
Nico Huber (Code Review)
gerrit at coreboot.org
Sat Jun 9 18:30:41 CEST 2018
Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/26974 )
Change subject: sb/intel/lynxpoint: Get rid of device_t
......................................................................
sb/intel/lynxpoint: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: I064ff5e76dd95c1770cd24139195b2a5fff2d382
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
Reviewed-on: https://review.coreboot.org/26974
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Nico Huber <nico.h at gmx.de>
---
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/pci.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/watchdog.c
5 files changed, 35 insertions(+), 31 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index d1d00c6..9d686de 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -109,9 +109,9 @@
* 0x80 - The PIRQ is not routed.
*/
-static void pch_pirq_init(device_t dev)
+static void pch_pirq_init(struct device *dev)
{
- device_t irq_dev;
+ struct device *irq_dev;
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -151,7 +151,7 @@
}
}
-static void pch_gpi_routing(device_t dev)
+static void pch_gpi_routing(struct device *dev)
{
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -180,7 +180,7 @@
pci_write_config32(dev, GPIO_ROUT, reg32);
}
-static void pch_power_options(device_t dev)
+static void pch_power_options(struct device *dev)
{
u8 reg8;
u16 reg16;
@@ -420,7 +420,7 @@
reg32 = RCBA32(HPTC);
}
-static void enable_clock_gating(device_t dev)
+static void enable_clock_gating(struct device *dev)
{
/* LynxPoint Mobile */
u32 reg32;
@@ -445,7 +445,7 @@
RCBA32_OR(0x38c0, 0x7); // SPI Dynamic
}
-static void enable_lp_clock_gating(device_t dev)
+static void enable_lp_clock_gating(struct device *dev)
{
/* LynxPoint LP */
u32 reg32;
@@ -595,7 +595,7 @@
pch_fixups(dev);
}
-static void pch_lpc_add_mmio_resources(device_t dev)
+static void pch_lpc_add_mmio_resources(struct device *dev)
{
u32 reg;
struct resource *res;
@@ -657,7 +657,8 @@
* Note: this function assumes there is no overlap with the default LPC device's
* claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
*/
-static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index)
+static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size,
+ int index)
{
struct resource *res;
@@ -670,7 +671,8 @@
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index)
+static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value,
+ int index)
{
/*
* Check if the register is enabled. If so and the base exceeds the
@@ -683,7 +685,7 @@
}
}
-static void pch_lpc_add_io_resources(device_t dev)
+static void pch_lpc_add_io_resources(struct device *dev)
{
struct resource *res;
config_t *config = dev->chip_info;
@@ -708,7 +710,7 @@
pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC);
}
-static void pch_lpc_read_resources(device_t dev)
+static void pch_lpc_read_resources(struct device *dev)
{
global_nvs_t *gnvs;
@@ -727,7 +729,7 @@
memset(gnvs, 0, sizeof(global_nvs_t));
}
-static void pch_lpc_enable(device_t dev)
+static void pch_lpc_enable(struct device *dev)
{
/* Enable PCH Display Port */
RCBA16(DISPBDF) = 0x0010;
@@ -736,7 +738,7 @@
pch_enable(dev);
}
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -747,7 +749,7 @@
}
}
-static void southbridge_inject_dsdt(device_t dev)
+static void southbridge_inject_dsdt(struct device *dev)
{
global_nvs_t *gnvs;
@@ -788,7 +790,7 @@
}
}
-static unsigned long southbridge_write_acpi_tables(device_t device,
+static unsigned long southbridge_write_acpi_tables(struct device *device,
unsigned long start,
struct acpi_rsdp *rsdp)
{
diff --git a/src/southbridge/intel/lynxpoint/pci.c b/src/southbridge/intel/lynxpoint/pci.c
index e2e052b..3c43210 100644
--- a/src/southbridge/intel/lynxpoint/pci.c
+++ b/src/southbridge/intel/lynxpoint/pci.c
@@ -104,7 +104,7 @@
ich_pci_dev_enable_resources(dev);
}
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
/* NOTE: This is not the default position! */
if (!vendor || !device) {
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 73c81b4..a7966f1 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -42,7 +42,7 @@
int coalesce;
int gbe_port;
int num_ports;
- device_t ports[MAX_NUM_ROOT_PORTS];
+ struct device *ports[MAX_NUM_ROOT_PORTS];
};
static struct root_port_config rpc;
@@ -55,18 +55,18 @@
return H_NUM_ROOT_PORTS;
}
-static inline int root_port_is_first(device_t dev)
+static inline int root_port_is_first(struct device *dev)
{
return PCI_FUNC(dev->path.pci.devfn) == 0;
}
-static inline int root_port_is_last(device_t dev)
+static inline int root_port_is_last(struct device *dev)
{
return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1);
}
/* Root ports are numbered 1..N in the documentation. */
-static inline int root_port_number(device_t dev)
+static inline int root_port_number(struct device *dev)
{
return PCI_FUNC(dev->path.pci.devfn) + 1;
}
@@ -101,7 +101,7 @@
}
}
-static void root_port_init_config(device_t dev)
+static void root_port_init_config(struct device *dev)
{
int rp;
@@ -154,7 +154,7 @@
/* Update devicetree with new Root Port function number assignment */
static void pch_pcie_device_set_func(int index, int pci_func)
{
- device_t dev;
+ struct device *dev;
unsigned new_devfn;
dev = rpc.ports[index];
@@ -187,7 +187,7 @@
enabled_ports = 0;
for (i = 0; i < rpc.num_ports; i++) {
- device_t dev;
+ struct device *dev;
int rp;
dev = rpc.ports[i];
@@ -275,7 +275,7 @@
pcie_enable_clock_gating();
for (i = 0; i < rpc.num_ports; i++) {
- device_t dev;
+ struct device *dev;
u32 reg32;
dev = rpc.ports[i];
@@ -328,7 +328,7 @@
RCBA32(RPFN) = rpc.new_rpfn;
}
-static void root_port_mark_disable(device_t dev)
+static void root_port_mark_disable(struct device *dev)
{
/* Mark device as disabled. */
dev->enabled = 0;
@@ -336,7 +336,7 @@
rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));
}
-static void root_port_check_disable(device_t dev)
+static void root_port_check_disable(struct device *dev)
{
int rp;
int is_lp;
@@ -695,7 +695,7 @@
pci_write_config16(dev, 0x1e, reg16);
}
-static void pch_pcie_enable(device_t dev)
+static void pch_pcie_enable(struct device *dev)
{
/* Add this device to the root port config structure. */
root_port_init_config(dev);
@@ -715,7 +715,8 @@
root_port_commit_config();
}
-static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pcie_set_subsystem(struct device *dev, unsigned vendor,
+ unsigned device)
{
/* NOTE: This is not the default position! */
if (!vendor || !device) {
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index c45579b..30e8aa8 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -301,7 +301,7 @@
pci_write_config32(dev, 0x300, reg32);
}
-static void sata_enable(device_t dev)
+static void sata_enable(struct device *dev)
{
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -322,7 +322,8 @@
pci_write_config16(dev, 0x90, map);
}
-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void sata_set_subsystem(struct device *dev, unsigned vendor,
+ unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/lynxpoint/watchdog.c b/src/southbridge/intel/lynxpoint/watchdog.c
index 74f69b0..9a867e4 100644
--- a/src/southbridge/intel/lynxpoint/watchdog.c
+++ b/src/southbridge/intel/lynxpoint/watchdog.c
@@ -28,7 +28,7 @@
//
void watchdog_off(void)
{
- device_t dev;
+ struct device *dev;
unsigned long value, base;
/* Turn off the ICH7 watchdog. */
--
To view, visit https://review.coreboot.org/26974
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I064ff5e76dd95c1770cd24139195b2a5fff2d382
Gerrit-Change-Number: 26974
Gerrit-PatchSet: 3
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
Gerrit-Reviewer: Nico Huber <nico.h at gmx.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180609/8d1990b9/attachment.html>
More information about the coreboot-gerrit
mailing list