[coreboot-gerrit] Change in coreboot[master]: mainboard/google/kahlee: Use 66MHz SPI clock for fast read

[Martin Roth (Code Review)]

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/26950


Change subject: mainboard/google/kahlee: Use 66MHz SPI clock for fast read
......................................................................

mainboard/google/kahlee: Use 66MHz SPI clock for fast read

Looking at the 100MHz signal, we were violating the timing requirements.
66MHz still isn't great, but it's a good tradeoff between improving
the signal and losing boot speed time.

This slows down the boot time by about 20mS.

BUG=b:109583457
TEST=Boot grunt, look at signal on scope

Change-Id: I7ce70c992822dd17c5877226e74c1890660768c6
Signed-off-by: Martin Roth <martinroth at google.com>
---
M src/mainboard/google/kahlee/bootblock/bootblock.c
1 file changed, 1 insertion(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/26950/1

diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c
index 8f124b3..7e6524d 100644
--- a/src/mainboard/google/kahlee/bootblock/bootblock.c
+++ b/src/mainboard/google/kahlee/bootblock/bootblock.c
@@ -44,7 +44,7 @@
 
 	/* Set SPI speeds before verstage. Needed for TPM */
 	sb_set_spi100(SPI_SPEED_33M,		/* Normal */
-			SPI_SPEED_100M,		/* Fast   */
+			SPI_SPEED_66M,		/* Fast   */
 			SPI_SPEED_66M,		/* AltIO  */
 			SPI_SPEED_66M);		/* TPM    */
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7ce70c992822dd17c5877226e74c1890660768c6
Gerrit-Change-Number: 26950
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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