[coreboot-gerrit] Change in coreboot[master]: cpu/intel/car/non-evict: Prepare for some POSTCAR_STAGE support

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/26789

to look at the new patch set (#2).

Change subject: cpu/intel/car/non-evict: Prepare for some POSTCAR_STAGE support
......................................................................

cpu/intel/car/non-evict: Prepare for some POSTCAR_STAGE support

Prepare a common cache as ram for CPU's featuring a Non eviction mode
MSR.

Change-Id: I7fa3853498856050855b3b97546f4d31f66d12f7
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
A src/cpu/intel/car/non-evict/cache_as_ram.S
A src/cpu/intel/car/non-evict/exit_car.S
M src/cpu/intel/haswell/Makefile.inc
M src/cpu/intel/model_2065x/Makefile.inc
M src/cpu/intel/model_206ax/Makefile.inc
5 files changed, 264 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/26789/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I7fa3853498856050855b3b97546f4d31f66d12f7
Gerrit-Change-Number: 26789
Gerrit-PatchSet: 2
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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