[coreboot-gerrit] Change in coreboot[master]: nb/intel/pineview: Switch to POSTCAR_STAGE

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26786


Change subject: nb/intel/pineview: Switch to POSTCAR_STAGE
......................................................................

nb/intel/pineview: Switch to POSTCAR_STAGE

Change-Id: If23925e2837645c974e4094e7e2d90e700d3d9e8
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/socket_FCBGA559/Makefile.inc
M src/northbridge/intel/pineview/Kconfig
M src/northbridge/intel/pineview/Makefile.inc
M src/northbridge/intel/pineview/ram_calc.c
4 files changed, 12 insertions(+), 11 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/26786/1

diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc
index 7c37019..7993294 100644
--- a/src/cpu/intel/socket_FCBGA559/Makefile.inc
+++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc
@@ -8,10 +8,7 @@
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
-ifneq ($(CONFIG_POSTCAR_STAGE),y)
-cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-else
 cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
 postcar-y += ../car/p4-netburst/exit_car.S
-endif
+
 romstage-y += ../car/romstage.c
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index e8ef9d9..80f566a 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -29,6 +29,8 @@
 	select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT
 	select RELOCATABLE_RAMSTAGE
 	select INTEL_GMA_ACPI
+	select POSTCAR_STAGE
+	select POSTCAR_CONSOLE
 
 config BOOTBLOCK_NORTHBRIDGE_INIT
 	string
diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc
index a4c08c8..d7936c1 100644
--- a/src/northbridge/intel/pineview/Makefile.inc
+++ b/src/northbridge/intel/pineview/Makefile.inc
@@ -25,4 +25,6 @@
 romstage-y += raminit.c
 romstage-y += early_init.c
 
+postcar-y += ram_calc.c
+
 endif
diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c
index e98ad71..32eabe4 100644
--- a/src/northbridge/intel/pineview/ram_calc.c
+++ b/src/northbridge/intel/pineview/ram_calc.c
@@ -107,9 +107,10 @@
 
 #define ROMSTAGE_RAM_STACK_SIZE 0x5000
 
-/* setup_stack_and_mtrrs() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use. */
-void *setup_stack_and_mtrrs(void)
+/* platform_enter_postcar() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use,
+ * and continues execution in postcar stage. */
+void platform_enter_postcar(void)
 {
 	struct postcar_frame pcf;
 	uintptr_t top_of_ram;
@@ -133,8 +134,7 @@
 	postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
 	postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
 
-	/* Save the number of MTRRs to setup. Return the stack location
-	 * pointing to the number of MTRRs.
-	 */
-	return postcar_commit_mtrrs(&pcf);
+	run_postcar_phase(&pcf);
+
+	/* We do not return here. */
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If23925e2837645c974e4094e7e2d90e700d3d9e8
Gerrit-Change-Number: 26786
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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