[coreboot-gerrit] Change in coreboot[master]: drivers/tpm: Add TPM ramstage driver for devices without vboot.
Philipp Deppenwiese (Code Review)
gerrit at coreboot.org
Wed Jul 25 17:53:38 CEST 2018
Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/24905 )
Change subject: drivers/tpm: Add TPM ramstage driver for devices without vboot.
......................................................................
drivers/tpm: Add TPM ramstage driver for devices without vboot.
Logic: If vboot is not used and the tpm is not initialized in the
romstage makes use of the ramstage driver to initialize the TPM
globally without having setup calls in lower SoC level implementations.
* Add TPM driver in ramstage chip init which calls the tpm_setup
function.
* Purge all occurrences of TPM init code and headers.
* Only compile TIS drivers into ramstage except for vboot usage.
* Remove Google Urara/Rotor TPM support because of missing i2c driver
in ramstage.
Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e
Signed-off-by: Philipp Deppenwiese <zaolin at das-labor.org>
Reviewed-on: https://review.coreboot.org/24905
Reviewed-by: Patrick Rudolph <siro at das-labor.org>
Reviewed-by: Felix Held <felix-coreboot at felixheld.de>
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
---
M src/cpu/intel/haswell/romstage.c
M src/drivers/intel/fsp1_1/romstage.c
A src/drivers/tpm/Kconfig
A src/drivers/tpm/Makefile.inc
A src/drivers/tpm/tpm.c
M src/mainboard/asus/kgpe-d16/romstage.c
M src/mainboard/google/link/romstage.c
M src/mainboard/google/parrot/romstage.c
M src/mainboard/google/rotor/Kconfig
M src/mainboard/google/stout/romstage.c
M src/mainboard/google/urara/Kconfig
M src/mainboard/intel/emeraldlake2/romstage.c
M src/mainboard/lenovo/x201/romstage.c
M src/mainboard/pcengines/apu2/romstage.c
M src/mainboard/samsung/lumpy/romstage.c
M src/mainboard/samsung/stumpy/romstage.c
M src/northbridge/intel/sandybridge/romstage.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/braswell/romstage/romstage.c
M src/soc/intel/broadwell/romstage/romstage.c
20 files changed, 43 insertions(+), 48 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
Patrick Rudolph: Looks good to me, but someone else must approve
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 0e91dae..b30d4af 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -42,7 +42,6 @@
#include "northbridge/intel/haswell/raminit.h"
#include "southbridge/intel/lynxpoint/pch.h"
#include "southbridge/intel/lynxpoint/me.h"
-#include <security/tpm/tspi.h>
#include <cpu/intel/romstage.h>
static inline void reset_system(void)
@@ -157,6 +156,4 @@
romstage_handoff_init(wake_from_s3);
post_code(0x3f);
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(wake_from_s3);
}
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 0320bf5..51f9a75 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -37,7 +37,6 @@
#include <stage_cache.h>
#include <string.h>
#include <timestamp.h>
-#include <security/tpm/tspi.h>
#include <vendorcode/google/chromeos/chromeos.h>
asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
@@ -167,15 +166,6 @@
if (romstage_handoff_init(
params->power_state->prev_sleep_state == ACPI_S3) < 0)
hard_reset();
-
- /*
- * Initialize the TPM, unless the TPM was already initialized
- * in verstage and used to verify romstage.
- */
- if ((IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) &&
- !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK))
- tpm_setup(params->power_state->prev_sleep_state ==
- ACPI_S3);
}
void after_cache_as_ram_stage(void)
diff --git a/src/drivers/tpm/Kconfig b/src/drivers/tpm/Kconfig
new file mode 100644
index 0000000..8508210
--- /dev/null
+++ b/src/drivers/tpm/Kconfig
@@ -0,0 +1,7 @@
+config TPM_INIT
+ bool
+ default y if TPM1 || TPM2
+ depends on !VBOOT
+ help
+ This driver automatically initializes the TPM if vboot is not used.
+ The TPM driver init is done during the ramstage chip init phase.
diff --git a/src/drivers/tpm/Makefile.inc b/src/drivers/tpm/Makefile.inc
new file mode 100644
index 0000000..4e80600
--- /dev/null
+++ b/src/drivers/tpm/Makefile.inc
@@ -0,0 +1 @@
+ramstage-$(CONFIG_TPM_INIT) += tpm.c
diff --git a/src/drivers/tpm/tpm.c b/src/drivers/tpm/tpm.c
new file mode 100644
index 0000000..e4a81c3
--- /dev/null
+++ b/src/drivers/tpm/tpm.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Facebook Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <stddef.h>
+#include <bootstate.h>
+#include <security/tpm/tspi.h>
+
+#if IS_ENABLED(CONFIG_ARCH_X86)
+#include <arch/acpi.h>
+#endif
+
+static void init_tpm_dev(void *unused)
+{
+#if IS_ENABLED(CONFIG_ARCH_X86)
+ int s3resume = acpi_is_wakeup_s3();
+ tpm_setup(s3resume);
+#else
+ tpm_setup(false);
+#endif
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, init_tpm_dev, NULL);
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
index 6188fcc..95fe630 100644
--- a/src/mainboard/asus/kgpe-d16/romstage.c
+++ b/src/mainboard/asus/kgpe-d16/romstage.c
@@ -46,7 +46,6 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include <security/tpm/tspi.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
@@ -624,9 +623,6 @@
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x54, 0x0707);
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0);
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0);
-
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(s3resume);
}
/**
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index d9f00f4..d7bf7c1 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -35,7 +35,6 @@
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h>
-#include <security/tpm/tspi.h>
#include <cbfs.h>
#include <southbridge/intel/bd82x6x/chip.h>
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 6163c35..782d6e5 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -35,7 +35,6 @@
#include <cpu/x86/msr.h>
#include <halt.h>
#include <cbfs.h>
-#include <security/tpm/tspi.h>
#include "ec/compal/ene932/ec.h"
void pch_enable_lpc(void)
diff --git a/src/mainboard/google/rotor/Kconfig b/src/mainboard/google/rotor/Kconfig
index 7a86493..437fa02 100644
--- a/src/mainboard/google/rotor/Kconfig
+++ b/src/mainboard/google/rotor/Kconfig
@@ -20,8 +20,6 @@
select SOC_MARVELL_MVMAP2315
select MAINBOARD_HAS_CHROMEOS
select BOARD_ROMSIZE_KB_4096
- select MAINBOARD_HAS_I2C_TPM_GENERIC
- select MAINBOARD_HAS_TPM1
config VBOOT
select VBOOT_MOCK_SECDATA
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 36ebcf7..f64e012 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -35,7 +35,6 @@
#include <cpu/x86/msr.h>
#include <halt.h>
#include <bootmode.h>
-#include <security/tpm/tspi.h>
#include <cbfs.h>
#include <ec/quanta/it8518/ec.h>
#include "ec.h"
diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig
index 2c4431c..3d415c4 100644
--- a/src/mainboard/google/urara/Kconfig
+++ b/src/mainboard/google/urara/Kconfig
@@ -24,8 +24,6 @@
select CPU_IMGTEC_PISTACHIO
select COMMON_CBFS_SPI_WRAPPER
select SPI_FLASH
- select MAINBOARD_HAS_I2C_TPM_GENERIC
- select MAINBOARD_HAS_TPM1
config MAINBOARD_DIR
string
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 9f46fe2..bdda191 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -35,7 +35,6 @@
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h>
-#include <security/tpm/tspi.h>
#define SIO_PORT 0x164e
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index d93cb8c..d4c60dd 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -35,7 +35,6 @@
#include <timestamp.h>
#include <arch/acpi.h>
#include <cbmem.h>
-#include <security/tpm/tspi.h>
#include "dock.h"
#include "arch/early_variables.h"
@@ -282,7 +281,4 @@
if (!s3resume)
quick_ram_check();
-
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(s3resume);
}
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index 7ea89b8..e35afc0 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -33,7 +33,6 @@
#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>
#include <Fch/Fch.h>
-#include <security/tpm/tspi.h>
#include "gpio_ftns.h"
@@ -103,9 +102,6 @@
post_code(0x41);
AGESAWRAPPER(amdinitenv);
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(false);
-
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
}
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index cea206a..3f655da 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -28,7 +28,6 @@
#include <cbmem.h>
#include <console/console.h>
#include <bootmode.h>
-#include <security/tpm/tspi.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index f502cc3..ffaff42 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -37,7 +37,6 @@
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h>
-#include <security/tpm/tspi.h>
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
#include <superio/smsc/lpc47n207/lpc47n207.h>
#endif
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 3bfefb9..3e128cd 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -28,7 +28,6 @@
#include <device/pci_def.h>
#include <device/device.h>
#include <halt.h>
-#include <security/tpm/tspi.h>
#include <northbridge/intel/sandybridge/chip.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
@@ -117,8 +116,5 @@
northbridge_romstage_finalize(s3resume);
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(s3resume);
-
post_code(0x3f);
}
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index c971b35..027e0d8 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -30,7 +30,6 @@
#include <stage_cache.h>
#include <string.h>
#include <timestamp.h>
-#include <security/tpm/tspi.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
@@ -228,9 +227,6 @@
timestamp_add_now(TS_AFTER_INITRAM);
romstage_handoff_init(prev_sleep_state == ACPI_S3);
-
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(prev_sleep_state == ACPI_S3);
}
void asmlinkage romstage_after_car(void)
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 2fbe406..f485dfd 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -43,7 +43,6 @@
#include <soc/romstage.h>
#include <soc/smm.h>
#include <soc/spi.h>
-#include <security/tpm/tspi.h>
void program_base_addresses(void)
{
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 1e2aa22..142f3b3 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -26,7 +26,6 @@
#include <cbmem.h>
#include <cpu/x86/mtrr.h>
#include <elog.h>
-#include <security/tpm/tspi.h>
#include <program_loading.h>
#include <romstage_handoff.h>
#include <stage_cache.h>
@@ -110,9 +109,6 @@
timestamp_add_now(TS_AFTER_INITRAM);
romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3);
-
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(params->power_state->prev_sleep_state == ACPI_S3);
}
asmlinkage void romstage_after_car(void)
--
To view, visit https://review.coreboot.org/24905
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e
Gerrit-Change-Number: 24905
Gerrit-PatchSet: 19
Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki at gmail.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: David Hendricks <david.hendricks at gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot at felixheld.de>
Gerrit-Reviewer: Julius Werner <jwerner at chromium.org>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph at 9elements.com>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki at gmail.com>
Gerrit-Reviewer: Piotr Król <piotr.krol at 3mdeb.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-CC: Kyösti Mälkki <kyosti.malkki at gmail.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180725/e79f4a1b/attachment.html>
More information about the coreboot-gerrit
mailing list