[coreboot-gerrit] Change in coreboot[master]: mb/google/poppy/variants/rammus: Add support for rammus board
Zhuohao Lee (Code Review)
gerrit at coreboot.org
Thu Jul 19 12:25:52 CEST 2018
Zhuohao Lee has uploaded this change for review. ( https://review.coreboot.org/27547
Change subject: mb/google/poppy/variants/rammus: Add support for rammus board
......................................................................
mb/google/poppy/variants/rammus: Add support for rammus board
This change adds variant rammus derived from baseboard poppy.
The setting is copied from the poppy and will be modified later
Change-Id: I169c225e28183a7a93f1142a3bf87a60b26ce9ca
Signed-off-by: Zhuohao Lee <zhuohao at chromium.org>
---
M src/mainboard/google/poppy/Kconfig
M src/mainboard/google/poppy/Kconfig.name
A src/mainboard/google/poppy/variants/rammus/Makefile.inc
A src/mainboard/google/poppy/variants/rammus/devicetree.cb
A src/mainboard/google/poppy/variants/rammus/gpio.c
A src/mainboard/google/poppy/variants/rammus/include/variant/acpi/camera.asl
A src/mainboard/google/poppy/variants/rammus/include/variant/acpi/dptf.asl
A src/mainboard/google/poppy/variants/rammus/include/variant/ec.h
A src/mainboard/google/poppy/variants/rammus/include/variant/gpio.h
A src/mainboard/google/poppy/variants/rammus/memory.c
A src/mainboard/google/poppy/variants/rammus/nhlt.c
11 files changed, 1,121 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/27547/1
diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig
index b2ff703..2ce3a81 100644
--- a/src/mainboard/google/poppy/Kconfig
+++ b/src/mainboard/google/poppy/Kconfig
@@ -30,6 +30,7 @@
default "variants/nami/devicetree.cb" if BOARD_GOOGLE_NAMI
default "variants/nautilus/devicetree.cb" if BOARD_GOOGLE_NAUTILUS
default "variants/nocturne/devicetree.cb" if BOARD_GOOGLE_NOCTURNE
+ default "variants/rammus/devicetree.cb" if BOARD_GOOGLE_RAMMUS
default "variants/soraka/devicetree.cb" if BOARD_GOOGLE_SORAKA
default "variants/baseboard/devicetree.cb"
@@ -53,6 +54,7 @@
default "NAMI TEST 1669" if BOARD_GOOGLE_NAMI
default "NAUTILUS TEST 3013" if BOARD_GOOGLE_NAUTILUS
default "NOCTURNE TEST 3421" if BOARD_GOOGLE_NOCTURNE
+ default "RAMMUS TEST 2130" if BOARD_GOOGLE_RAMMUS
default "SORAKA TEST 1869" if BOARD_GOOGLE_SORAKA
config INCLUDE_NHLT_BLOBS
@@ -85,6 +87,13 @@
select NHLT_DMIC_4CH
select NHLT_MAX98373
+config INCLUDE_NHLT_BLOBS_RAMMUS
+ bool "Include blobs for rammus audio."
+ select NHLT_DMIC_2CH
+ select NHLT_DMIC_4CH
+ select NHLT_MAX98927
+ select NHLT_RT5663
+
config MAINBOARD_DIR
string
default "google/poppy"
@@ -96,6 +105,7 @@
default "Google_Nami" if BOARD_GOOGLE_NAMI
default "Google_Nautilus" if BOARD_GOOGLE_NAUTILUS
default "Google_Nocturne" if BOARD_GOOGLE_NOCTURNE
+ default "Google_Rammus" if BOARD_GOOGLE_RAMMUS
default "Google_Soraka" if BOARD_GOOGLE_SORAKA
config MAINBOARD_PART_NUMBER
@@ -105,6 +115,7 @@
default "Nami" if BOARD_GOOGLE_NAMI
default "Nautilus" if BOARD_GOOGLE_NAUTILUS
default "Nocturne" if BOARD_GOOGLE_NOCTURNE
+ default "Rammus" if BOARD_GOOGLE_RAMMUS
default "Soraka" if BOARD_GOOGLE_SORAKA
config MAX_CPUS
@@ -126,6 +137,7 @@
default "nami" if BOARD_GOOGLE_NAMI
default "nautilus" if BOARD_GOOGLE_NAUTILUS
default "nocturne" if BOARD_GOOGLE_NOCTURNE
+ default "rammus" if BOARD_GOOGLE_RAMMUS
default "soraka" if BOARD_GOOGLE_SORAKA
# Select this option to enable camera ACPI support on the variant.
@@ -178,6 +190,13 @@
select MAINBOARD_HAS_SPI_TPM_CR50
select VARIANT_HAS_CAMERA_ACPI
+config VARIANT_SPECIFIC_OPTIONS_RAMMUS
+ def_bool n
+ select DRIVERS_I2C_MAX98927
+ select NO_FADT_8042
+ select VARIANT_HAS_CAMERA_ACPI
+ select MAINBOARD_HAS_I2C_TPM_CR50
+
config VARIANT_SPECIFIC_OPTIONS_SORAKA
def_bool n
select DRIVERS_I2C_MAX98927
diff --git a/src/mainboard/google/poppy/Kconfig.name b/src/mainboard/google/poppy/Kconfig.name
index 65e658b..c33d7fb 100644
--- a/src/mainboard/google/poppy/Kconfig.name
+++ b/src/mainboard/google/poppy/Kconfig.name
@@ -25,6 +25,11 @@
select BOARD_GOOGLE_BASEBOARD_POPPY
select VARIANT_SPECIFIC_OPTIONS_NOCTURNE
+config BOARD_GOOGLE_RAMMUS
+ bool "-> Rammus"
+ select BOARD_GOOGLE_BASEBOARD_POPPY
+ select VARIANT_SPECIFIC_OPTIONS_RAMMUS
+
config BOARD_GOOGLE_SORAKA
bool "-> Soraka"
select BOARD_GOOGLE_BASEBOARD_POPPY
diff --git a/src/mainboard/google/poppy/variants/rammus/Makefile.inc b/src/mainboard/google/poppy/variants/rammus/Makefile.inc
new file mode 100644
index 0000000..d265367
--- /dev/null
+++ b/src/mainboard/google/poppy/variants/rammus/Makefile.inc
@@ -0,0 +1,9 @@
+
+SPD_SOURCES = empty # 0b0000
+
+bootblock-y += gpio.c
+
+romstage-y += memory.c
+
+ramstage-y += gpio.c
+ramstage-y += nhlt.c
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
new file mode 100644
index 0000000..ad1e628
--- /dev/null
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -0,0 +1,412 @@
+chip soc/intel/skylake
+
+ # Deep Sx states
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "0"
+ register "deep_s5_enable_ac" = "1"
+ register "deep_s5_enable_dc" = "1"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_B"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
+ # Enable DPTF
+ register "dptf_enable" = "1"
+
+ # Enable S0ix
+ register "s0ix_enable" = "1"
+
+ # FSP Configuration
+ register "ProbelessTrace" = "0"
+ register "EnableLan" = "0"
+ register "EnableSata" = "0"
+ register "SataSalpSupport" = "0"
+ register "SataMode" = "0"
+ register "SataPortsEnable[0]" = "0"
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "1"
+ register "IoBufferOwnership" = "3"
+ register "EnableTraceHub" = "0"
+ register "SsicPortEnable" = "0"
+ register "SmbusEnable" = "1"
+ register "Cio2Enable" = "1"
+ register "SaImguEnable" = "1"
+ register "ScsEmmcEnabled" = "1"
+ register "ScsEmmcHs400Enabled" = "1"
+ register "ScsSdCardEnabled" = "2"
+ register "PttSwitch" = "0"
+ register "InternalGfx" = "1"
+ register "SkipExtGfxScan" = "1"
+ register "Device4Enable" = "1"
+ register "HeciEnabled" = "0"
+ register "SaGv" = "3"
+ register "SerialIrqConfigSirqEnable" = "1"
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "1" # 1s
+ register "PmConfigSlpSusMinAssert" = "1" # 500ms
+ register "PmConfigSlpAMinAssert" = "3" # 2s
+ register "PmTimerDisabled" = "1"
+ register "VmxEnable" = "1"
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ # VR Settings Configuration for 4 Domains
+ #+----------------+-------+-------+-------+-------+
+ #| Domain/Setting | SA | IA | GTUS | GTS |
+ #+----------------+-------+-------+-------+-------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 2A | 2A | 2A | 2A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| IccMax | 5A | 24A | 24A | 24A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #| AcLoadline | 15 | 5.7 | 5.5 | 5.5 |
+ #| DcLoadline | 14.3 | 4.83 | 4.2 | 4.2 |
+ #+----------------+-------+-------+-------+-------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(2),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(5),
+ .voltage_limit = 1520,
+ .ac_loadline = 1500,
+ .dc_loadline = 1430,
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(2),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(24),
+ .voltage_limit = 1520,
+ .ac_loadline = 570,
+ .dc_loadline = 483,
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(2),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(24),
+ .voltage_limit = 1520,
+ .ac_loadline = 550,
+ .dc_loadline = 420,
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(2),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(24),
+ .voltage_limit = 1520,
+ .ac_loadline = 550,
+ .dc_loadline = 420,
+ }"
+
+ # Enable Root port 1.
+ register "PcieRpEnable[0]" = "1"
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[0]" = "1"
+ # RP 1 uses SRCCLKREQ1#
+ register "PcieRpClkReqNumber[0]" = "1"
+ # RP 1, Enable Advanced Error Reporting
+ register "PcieRpAdvancedErrorReporting[0]" = "1"
+ # RP 1, Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[0]" = "1"
+ # RP 1 uses uses CLK SRC 1
+ register "PcieRpClkSrcNumber[0]" = "1"
+
+ register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+ register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port
+ register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
+ #| I2C0 | Touchscreen |
+ #| I2C1 | H1 |
+ #| I2C2 | Camera |
+ #| I2C3 | Pen |
+ #| I2C4 | Camera |
+ #| I2C5 | Audio |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 185,
+ .scl_hcnt = 90,
+ .sda_hold = 36,
+ },
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 190,
+ .scl_hcnt = 100,
+ .sda_hold = 36,
+ },
+ .early_init = 1,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 190,
+ .scl_hcnt = 97,
+ .sda_hold = 36,
+ },
+ },
+ .i2c[4] = {
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 190,
+ .scl_hcnt = 97,
+ .sda_hold = 36,
+ },
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 190,
+ .scl_hcnt = 98,
+ .sda_hold = 36,
+ },
+ },
+ }"
+
+ # Touchscreen
+ register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
+
+ # H1
+ register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"
+
+ # Camera
+ register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"
+
+ # Pen
+ register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8"
+
+ # Camera
+ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
+
+ # Audio
+ register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8"
+
+ # Must leave UART0 enabled or SD/eMMC will not work as PCI
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoPci,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled,
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart0] = PchSerialIoPci,
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
+ }"
+
+ register "speed_shift_enable" = "1"
+ register "psys_pmax" = "45"
+ # PL2 override 15W for KBL-Y
+ register "tdp_pl2_override" = "15"
+ register "tcc_offset" = "10" # TCC of 90C
+
+ # Use default SD card detect GPIO configuration
+ register "sdcard_cd_gpio_default" = "GPP_E15"
+
+ # PCH Trip Temperature in degree C
+ register "pch_trip_temp" = "75"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 on end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 15.0 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0001""
+ register "desc" = ""ELAN Touchscreen""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
+ register "probed" = "1"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)"
+ register "reset_delay_ms" = "20"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)"
+ register "enable_delay_ms" = "1"
+ register "has_power_resource" = "1"
+ device i2c 10 on end
+ end
+ chip drivers/i2c/generic
+ register "hid" = ""ATML0001""
+ register "desc" = ""Atmel Touchscreen""
+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
+ register "probed" = "1"
+ register "has_power_resource" = "1"
+ register "disable_gpio_export_in_crs" = "1"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)"
+ register "enable_delay_ms" = "250"
+ device i2c 4b on end
+ end
+ end # I2C #0
+ device pci 15.1 on
+ chip drivers/i2c/tpm
+ register "hid" = ""GOOG0005""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
+ device i2c 50 on end
+ end
+ end # I2C #1
+ device pci 15.2 on end # I2C #2
+ device pci 15.3 on
+ chip drivers/i2c/hid
+ register "generic.hid" = ""WCOM50C1""
+ register "generic.desc" = ""WCOM Digitizer""
+ register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D1_IRQ)"
+ register "generic.wake" = "GPE0_DW1_12"
+ register "hid_desc_reg_offset" = "0x1"
+ device i2c 0x9 on end
+ end
+ chip drivers/generic/gpio_keys
+ register "name" = ""PENH""
+ register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D8)"
+ register "key.dev_name" = ""EJCT""
+ register "key.linux_code" = "SW_PEN_INSERTED"
+ register "key.linux_input_type" = "EV_SW"
+ register "key.label" = ""pen_eject""
+ device generic 0 on end
+ end
+ end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 off end # SATA
+ device pci 19.0 on end # UART #2
+ device pci 19.1 on
+ chip drivers/i2c/max98927
+ register "interleave_mode" = "1"
+ register "vmon_slot_no" = "4"
+ register "imon_slot_no" = "5"
+ register "uid" = "0"
+ register "desc" = ""SSM4567 Right Speaker Amp""
+ register "name" = ""MAXR""
+ device i2c 39 on end
+ end
+ chip drivers/i2c/max98927
+ register "interleave_mode" = "1"
+ register "vmon_slot_no" = "6"
+ register "imon_slot_no" = "7"
+ register "uid" = "1"
+ register "desc" = ""SSM4567 Left Speaker Amp""
+ register "name" = ""MAXL""
+ device i2c 3A on end
+ end
+ chip drivers/i2c/generic
+ register "hid" = ""10EC5663""
+ register "name" = ""RT53""
+ register "desc" = ""Realtek RT5663""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)"
+ register "probed" = "1"
+ device i2c 13 on end
+ end
+ end # I2C #5
+ device pci 19.2 on end # I2C #4
+ device pci 1c.0 on
+ chip drivers/intel/wifi
+ register "wake" = "GPE0_DW0_00"
+ device pci 00.0 on end
+ end
+ end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 off end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1e.0 on end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1e.4 on end # eMMC
+ device pci 1e.5 off end # SDIO
+ device pci 1e.6 on end # SDCard
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # LPC Interface
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/google/poppy/variants/rammus/gpio.c b/src/mainboard/google/poppy/variants/rammus/gpio.c
new file mode 100644
index 0000000..d145841
--- /dev/null
+++ b/src/mainboard/google/poppy/variants/rammus/gpio.c
@@ -0,0 +1,405 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <compiler.h>
+
+/* Pad configuration in ramstage */
+/* Leave eSPI pins untouched from default settings */
+static const struct pad_config gpio_table[] = {
+ /* A0 : RCIN# ==> NC(TP41) */
+ PAD_CFG_NC(GPP_A0),
+ /* A1 : ESPI_IO0 */
+ /* A2 : ESPI_IO1 */
+ /* A3 : ESPI_IO2 */
+ /* A4 : ESPI_IO3 */
+ /* A5 : ESPI_CS# */
+ /* A6 : SERIRQ ==> NC(TP44) */
+ PAD_CFG_NC(GPP_A6),
+ /* A7 : PIRQA# ==> NC(TP29) */
+ PAD_CFG_NC(GPP_A7),
+ /* A8 : CLKRUN# ==> NC(TP45) */
+ PAD_CFG_NC(GPP_A8),
+ /* A9 : ESPI_CLK */
+ /* A10 : CLKOUT_LPC1 ==> NC */
+ PAD_CFG_NC(GPP_A10),
+ /* A11 : PME# ==> NC(TP67) */
+ PAD_CFG_NC(GPP_A11),
+ /* A12 : BM_BUSY# ==> NC */
+ PAD_CFG_NC(GPP_A12),
+ /* A13 : SUSWARN# ==> SUSWARN_L */
+ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+ /* A14 : ESPI_RESET# */
+ /* A15 : SUSACK# ==> SUSACK_L */
+ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+ /* A16 : SD_1P8_SEL ==> SD_PWR_1800_SEL */
+ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+ /* A17 : SD_PWR_EN# ==> EN_SD_SOCKET_PWR_L */
+ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
+ /* A18 : ISH_GP0 ==> NC */
+ PAD_CFG_NC(GPP_A18),
+ /* A19 : ISH_GP1 ==> NC */
+ PAD_CFG_NC(GPP_A19),
+ /* A20 : ISH_GP2 ==> ACCEL_GYRO_INT_L */
+ PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST),
+ /* A21 : ISH_GP3 ==> NC */
+ PAD_CFG_NC(GPP_A21),
+ /* A22 : ISH_GP4 ==> NC */
+ PAD_CFG_NC(GPP_A22),
+ /* A23 : ISH_GP5 ==> NC */
+ PAD_CFG_NC(GPP_A23),
+
+ /* B0 : CORE_VID0 ==> WLAN_PCIE_WAKE_L */
+ PAD_CFG_GPI_ACPI_SCI(GPP_B0, NONE, DEEP, INVERT),
+ /* B1 : CORE_VID1 ==> NC(TP43) */
+ PAD_CFG_NC(GPP_B1),
+ /* B2 : VRALERT# ==> NC */
+ PAD_CFG_NC(GPP_B2),
+ /* B3 : CPU_GP2 ==> NC */
+ PAD_CFG_NC(GPP_B3),
+ /* B4 : CPU_GP3 ==> NC */
+ PAD_CFG_NC(GPP_B4),
+ /* B5 : SRCCLKREQ0# ==> NC */
+ PAD_CFG_NC(GPP_B5),
+ /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */
+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+ /* B7 : SRCCLKREQ2# ==> WWAN_PCIE_CLKREQ_L */
+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+ /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */
+ PAD_CFG_GPO(GPP_B8, 0, RSMRST),
+ /* B9 : SRCCLKREQ4# ==> NC */
+ PAD_CFG_NC(GPP_B9),
+ /* B10 : SRCCLKREQ5# ==> NC */
+ PAD_CFG_NC(GPP_B10),
+ /* B11 : EXT_PWR_GATE# ==> NC */
+ PAD_CFG_NC(GPP_B11),
+ /* B12 : SLP_S0# ==> SLP_S0_L_G */
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+ /* B13 : PLTRST# ==> PLT_RST_L */
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+ /* B14 : SPKR ==> NC */
+ PAD_CFG_NC(GPP_B14),
+ /* B15 : GSPI0_CS# ==> NC */
+ PAD_CFG_NC(GPP_B15),
+ /* B16 : GSPI0_CLK ==> NC */
+ PAD_CFG_NC(GPP_B16),
+ /* B17 : GSPI0_MISO ==> NC */
+ PAD_CFG_NC(GPP_B17),
+ /* B18 : GSPI0_MOSI ==> NC */
+ PAD_CFG_NC(GPP_B18),
+ /* B19 : GSPI1_CS# ==> NC */
+ PAD_CFG_NC(GPP_B19),
+ /* B20 : GSPI1_CLK ==> NC */
+ PAD_CFG_NC(GPP_B20),
+ /* B21 : GSPI1_MISO ==> NC */
+ PAD_CFG_NC(GPP_B21),
+ /* B22 : GSPI1_MOSI ==> NC */
+ PAD_CFG_NC(GPP_B22),
+ /* B23 : SM1ALERT# ==> NC */
+ PAD_CFG_NC(GPP_B23),
+
+ /* C0 : SMBCLK ==> NC */
+ PAD_CFG_NC(GPP_C0),
+ /* C1 : SMBDATA ==> NC */
+ PAD_CFG_NC(GPP_C1),
+ /* C2 : SMBALERT# ==> NC */
+ PAD_CFG_NC(GPP_C2),
+ /* C3 : SML0CLK ==> NC */
+ PAD_CFG_NC(GPP_C3),
+ /* C4 : SML0DATA ==> NC */
+ PAD_CFG_NC(GPP_C4),
+ /* C5 : SML0ALERT# ==> NC */
+ PAD_CFG_NC(GPP_C5),
+ /* C6 : SM1CLK ==> EC_IN_RW_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP),
+ /* C7 : SM1DATA ==> NC */
+ PAD_CFG_NC(GPP_C7),
+ /* C8 : UART0_RXD ==> FP_INT */
+ PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST),
+ /* C9 : UART0_TXD ==> FP_RST_ODL */
+ PAD_CFG_GPO(GPP_C9, 0, DEEP),
+ /* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */
+ PAD_CFG_GPO(GPP_C10, 1, DEEP),
+ /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */
+ PAD_CFG_GPO(GPP_C11, 0, DEEP),
+ /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),
+ /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),
+ /* C14 : UART1_RTS# ==> PCH_MEM_CONFIG[2] */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),
+ /* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP),
+ /* C16 : I2C0_SDA ==> PCH_I2C0_TOUCHSCREEN_3V3_SDA */
+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+ /* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */
+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+ /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */
+ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+ /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */
+ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+ /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+ /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */
+ PAD_CFG_GPO(GPP_C22, 0, DEEP),
+ /* C23 : UART2_CTS# ==> PCH_WP */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
+
+ /* D0 : SPI1_CS# ==> EN_PP3300_DX_LTE */
+ PAD_CFG_GPO(GPP_D0, 1, DEEP),
+ /* D1 : SPI1_CLK ==> PEN_IRQ_L */
+ PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST),
+ /* D2 : SPI1_MISO ==> PEN_PDCT_L */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_D2, NONE, DEEP),
+ /* D3 : SPI1_MOSI ==> PEN_RST_L */
+ PAD_CFG_GPO(GPP_D3, 1, DEEP),
+ /* D4 : FASHTRIG ==> LTE_GPS_OFF_ODL */
+ PAD_CFG_GPO(GPP_D4, 1, DEEP),
+ /* D5 : ISH_I2C0_SDA ==> ISH_I2C_SENSOR_1V8_SDA */
+ PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1),
+ /* D6 : ISH_I2C0_SCL ==> ISH_I2C_SENSOR_1V8_SCL */
+ PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1),
+ /* D7 : ISH_I2C1_SDA ==> NC */
+ PAD_CFG_NC(GPP_D7),
+ /* D8 : ISH_I2C1_SCL ==> PEN_EJECT_ODL -- for notification */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_D8, 20K_PU, DEEP),
+ /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, PLTRST),
+ /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */
+ PAD_CFG_GPO(GPP_D10, 1, DEEP),
+ /* D11 : ISH_SPI_MISO ==> SPKR_INT_L */
+ PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST),
+ /* D12 : ISH_SPI_MOSI ==> PEN_EJECT_ODL -- for wake event */
+ PAD_CFG_GPI_ACPI_SCI(GPP_D12, 20K_PU, DEEP, INVERT),
+ /* D13 : ISH_UART0_RXD ==> NC */
+ PAD_CFG_NC(GPP_D13),
+ /* D14 : ISH_UART0_TXD ==> NC */
+ PAD_CFG_NC(GPP_D14),
+ /* D15 : ISH_UART0_RTS# ==> NC */
+ PAD_CFG_NC(GPP_D15),
+ /* D16 : ISH_UART0_CTS# ==> LTE_OFF_ODL */
+ PAD_CFG_GPO(GPP_D16, 1, DEEP),
+ /* D17 : DMIC_CLK1 */
+ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+ /* D18 : DMIC_DATA1 */
+ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+ /* D19 : DMIC_CLK0 */
+ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+ /* D20 : DMIC_DATA0 */
+ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+ /* D21 : SPI1_IO2 ==> LTE_BODY_SAR_ODL */
+ PAD_CFG_GPO(GPP_D21, 1, DEEP),
+ /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */
+ PAD_CFG_GPO(GPP_D22, 1, DEEP),
+ /* D23 : I2S_MCLK ==> I2S_MCLK_R */
+ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+
+ /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
+ /* E1 : SATAXPCIE1 ==> NC */
+ PAD_CFG_NC(GPP_E1),
+ /* E2 : SATAXPCIE2 ==> NC */
+ PAD_CFG_NC(GPP_E2),
+ /* E3 : CPU_GP0 ==> TOUCHSCREEN_RST_L */
+ PAD_CFG_GPO(GPP_E3, 0, DEEP),
+ /* E4 : SATA_DEVSLP0 ==> NC */
+ PAD_CFG_NC(GPP_E4),
+ /* E5 : SATA_DEVSLP1 ==> NC */
+ PAD_CFG_NC(GPP_E5),
+ /* E6 : SATA_DEVSLP2 ==> NC */
+ PAD_CFG_NC(GPP_E6),
+ /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */
+ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),
+ /* E8 : SATALED# ==> NC */
+ PAD_CFG_NC(GPP_E8),
+ /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */
+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+ /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */
+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+ /* E11 : USB2_OC2# ==> TOUCHSCREEN_RESET_L */
+ PAD_CFG_GPO(GPP_E11, 0, DEEP),
+ /* E12 : USB2_OC3# ==> USB2_OC3_L */
+ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+ /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */
+ PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1),
+ /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */
+ PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),
+ /* E15 : DDPD_HPD2 ==> SD_CD# */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, DEEP),
+ /* E16 : DDPE_HPD3 ==> NC(TP244) */
+ PAD_CFG_NC(GPP_E16),
+ /* E17 : EDP_HPD */
+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+ /* E18 : DDPB_CTRLCLK ==> NC */
+ PAD_CFG_NC(GPP_E18),
+ /* E19 : DDPB_CTRLDATA ==> NC */
+ PAD_CFG_NC(GPP_E19),
+ /* E20 : DDPC_CTRLCLK ==> NC */
+ PAD_CFG_NC(GPP_E20),
+ /* E21 : DDPC_CTRLDATA ==> NC */
+ PAD_CFG_NC(GPP_E21),
+ /* E22 : DDPD_CTRLCLK ==> NC */
+ PAD_CFG_NC(GPP_E22),
+ /* E23 : DDPD_CTRLDATA ==> NC */
+ PAD_CFG_NC(GPP_E23),
+
+ /* The next 4 pads are for bit banging the amplifiers, default to I2S */
+ /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),
+ /* F1 : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),
+ /* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),
+ /* F3 : I2S2_RXD ==> NC */
+ PAD_CFG_NC(GPP_F3),
+ /* F4 : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */
+ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),
+ /* F5 : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */
+ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1),
+ /* F6 : I2C3_SDA ==> PCH_I2C3_PEN_1V8_SDA */
+ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1),
+ /* F7 : I2C3_SCL ==> PCH_I2C3_PEN_1V8_SCL */
+ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1),
+ /* F8 : I2C4_SDA ==> PCH_I2C4_UFCAM_1V8_SDA */
+ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
+ /* F9 : I2C4_SCL ==> PCH_I2C4_UFCAM_1V8_SCL */
+ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
+ /* F10 : I2C5_SDA ==> PCH_I2C5_AUDIO_1V8_SDA */
+ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1),
+ /* F11 : I2C5_SCL ==> PCH_I2C5_AUDIO_1V8_SCL */
+ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1),
+ /* F12 : EMMC_CMD */
+ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+ /* F13 : EMMC_DATA0 */
+ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+ /* F14 : EMMC_DATA1 */
+ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+ /* F15 : EMMC_DATA2 */
+ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+ /* F16 : EMMC_DATA3 */
+ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+ /* F17 : EMMC_DATA4 */
+ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+ /* F18 : EMMC_DATA5 */
+ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
+ /* F19 : EMMC_DATA6 */
+ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+ /* F20 : EMMC_DATA7 */
+ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+ /* F21 : EMMC_RCLK */
+ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+ /* F22 : EMMC_CLK */
+ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+ /* F23 : RSVD ==> NC */
+ PAD_CFG_NC(GPP_F23),
+
+ /* G0 : SD_CMD */
+ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
+ /* G1 : SD_DATA0 */
+ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
+ /* G2 : SD_DATA1 */
+ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
+ /* G3 : SD_DATA2 */
+ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
+ /* G4 : SD_DATA3 */
+ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
+ /* G5 : SD_CD# */
+ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
+ /* G6 : SD_CLK */
+ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
+ /* G7 : SD_WP */
+ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1),
+
+ /* GPD0: BATLOW# ==> PCH_BATLOW_L */
+ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+ /* GPD1: ACPRESENT ==> EC_PCH_ACPRESENT */
+ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+ /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */
+ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
+ /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */
+ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
+ /* GPD4: SLP_S3# ==> SLP_S3_L */
+ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+ /* GPD5: SLP_S4# ==> SLP_S4_L */
+ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+ /* GPD6: SLP_A# ==> NC(TP26) */
+ PAD_CFG_NC(GPD6),
+ /* GPD7: RSVD ==> NC */
+ PAD_CFG_NC(GPD7),
+ /* GPD8: SUSCLK ==> PCH_SUSCLK */
+ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+ /* GPD9: SLP_WLAN# ==> NC(TP25) */
+ PAD_CFG_NC(GPD9),
+ /* GPD10: SLP_S5# ==> NC(TP15) */
+ PAD_CFG_NC(GPD10),
+ /* GPD11: LANPHYC ==> NC */
+ PAD_CFG_NC(GPD11),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+ /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */
+ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+ /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */
+ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+
+ /* Ensure UART pins are in native mode for H1. */
+ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+ /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+
+ /* C23 : UART2_CTS# ==> PCH_WP */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
+
+ /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
+};
+
+const struct pad_config * __weak variant_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+const struct pad_config * __weak
+ variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
+
+/* override specific gpio by sku id */
+const struct pad_config * __weak
+ variant_sku_gpio_table(size_t *num)
+{
+ *num = 0;
+ return NULL;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+const struct cros_gpio * __weak variant_cros_gpios(size_t *num)
+{
+ *num = ARRAY_SIZE(cros_gpios);
+ return cros_gpios;
+}
diff --git a/src/mainboard/google/poppy/variants/rammus/include/variant/acpi/camera.asl b/src/mainboard/google/poppy/variants/rammus/include/variant/acpi/camera.asl
new file mode 100644
index 0000000..dc280d6
--- /dev/null
+++ b/src/mainboard/google/poppy/variants/rammus/include/variant/acpi/camera.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/camera.asl>
diff --git a/src/mainboard/google/poppy/variants/rammus/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/rammus/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000..fda61a3
--- /dev/null
+++ b/src/mainboard/google/poppy/variants/rammus/include/variant/acpi/dptf.asl
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Google Inc.
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE 82
+#define DPTF_CPU_CRITICAL 100
+
+#define DPTF_TSR0_SENSOR_ID 1
+#define DPTF_TSR0_SENSOR_NAME "Ambient"
+#define DPTF_TSR0_PASSIVE 55
+#define DPTF_TSR0_CRITICAL 65
+#define DPTF_TSR0_TABLET_PASSIVE 55
+#define DPTF_TSR0_TABLET_CRITICAL 65
+
+#define DPTF_TSR1_SENSOR_ID 2
+#define DPTF_TSR1_SENSOR_NAME "Charger"
+#define DPTF_TSR1_PASSIVE 58
+#define DPTF_TSR1_CRITICAL 70
+#define DPTF_TSR1_TABLET_PASSIVE 60
+#define DPTF_TSR1_TABLET_CRITICAL 70
+
+#define DPTF_TSR2_SENSOR_ID 3
+#define DPTF_TSR2_SENSOR_NAME "DRAM"
+#define DPTF_TSR2_PASSIVE 60
+#define DPTF_TSR2_CRITICAL 75
+#define DPTF_TSR2_TABLET_PASSIVE 58
+#define DPTF_TSR2_TABLET_CRITICAL 75
+
+#define DPTF_TSR3_SENSOR_ID 4
+#define DPTF_TSR3_SENSOR_NAME "eMMC"
+#define DPTF_TSR3_PASSIVE 60
+#define DPTF_TSR3_CRITICAL 75
+#define DPTF_TSR3_TABLET_PASSIVE 58
+#define DPTF_TSR3_TABLET_CRITICAL 75
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+})
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
+
+ /* CPU Throttle Effect on Ambient (TSR0) */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 300, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Throttle Effect on Charger (TSR1) */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 300, 0, 0, 0, 0 },
+#endif
+
+ /* CPU Throttle Effect on DRAM (TSR2) */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 80, 0, 0, 0, 0 },
+
+ /* CPU Throttle Effect on eMMC (TSR3) */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 80, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 4500, /* PowerLimitMinimum */
+ 7000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 15000, /* PowerLimitMinimum */
+ 15000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 1000 /* StepSize */
+ }
+})
+
+/* Include DPTF */
+#include <soc/intel/skylake/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/poppy/variants/rammus/include/variant/ec.h b/src/mainboard/google/poppy/variants/rammus/include/variant/ec.h
new file mode 100644
index 0000000..9fed9e6
--- /dev/null
+++ b/src/mainboard/google/poppy/variants/rammus/include/variant/ec.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MAINBOARD_EC_H__
+#define __MAINBOARD_EC_H__
+
+#include <baseboard/ec.h>
+
+#define EC_ENABLE_TABLET_EVENT /* Tablet event to support DPTF */
+
+#endif /* __MAINBOARD_EC_H__ */
diff --git a/src/mainboard/google/poppy/variants/rammus/include/variant/gpio.h b/src/mainboard/google/poppy/variants/rammus/include/variant/gpio.h
new file mode 100644
index 0000000..cd34cf0
--- /dev/null
+++ b/src/mainboard/google/poppy/variants/rammus/include/variant/gpio.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/poppy/variants/rammus/memory.c b/src/mainboard/google/poppy/variants/rammus/memory.c
new file mode 100644
index 0000000..2009641
--- /dev/null
+++ b/src/mainboard/google/poppy/variants/rammus/memory.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <compiler.h>
+#include <gpio.h>
+#include <variant/gpio.h>
+
+/* DQ byte map */
+static const u8 dq_map[][12] = {
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
+ { 0xCC, 0x33, 0x00, 0x33, 0xCC, 0x33,
+ 0xCC, 0x00, 0xFF, 0x00, 0xFF, 0x00 }
+};
+
+/* DQS CPU<>DRAM map */
+static const u8 dqs_map[][8] = {
+ { 2, 3, 1, 0, 4, 7, 6, 5 },
+ { 5, 6, 0, 3, 4, 7, 2, 1 },
+};
+
+/* Rcomp resistor */
+static const u16 rcomp_resistor[] = { 200, 81, 162 };
+
+/* Rcomp target */
+static const u16 rcomp_target[] = { 100, 40, 40, 23, 40 };
+
+void __weak variant_memory_params(struct memory_params *p)
+{
+ p->type = MEMORY_LPDDR3;
+ p->dq_map = dq_map;
+ p->dq_map_size = sizeof(dq_map);
+ p->dqs_map = dqs_map;
+ p->dqs_map_size = sizeof(dqs_map);
+ p->rcomp_resistor = rcomp_resistor;
+ p->rcomp_resistor_size = sizeof(rcomp_resistor);
+ p->rcomp_target = rcomp_target;
+ p->rcomp_target_size = sizeof(rcomp_target);
+}
+
+int __weak variant_memory_sku(void)
+{
+ gpio_t spd_gpios[] = {
+ GPIO_MEM_CONFIG_0,
+ GPIO_MEM_CONFIG_1,
+ GPIO_MEM_CONFIG_2,
+ GPIO_MEM_CONFIG_3,
+ };
+
+ return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
diff --git a/src/mainboard/google/poppy/variants/rammus/nhlt.c b/src/mainboard/google/poppy/variants/rammus/nhlt.c
new file mode 100644
index 0000000..071976f
--- /dev/null
+++ b/src/mainboard/google/poppy/variants/rammus/nhlt.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <compiler.h>
+#include <console/console.h>
+#include <nhlt.h>
+#include <soc/nhlt.h>
+
+void __weak variant_nhlt_init(struct nhlt *nhlt)
+{
+ /* 2 Channel DMIC array. */
+ if (nhlt_soc_add_dmic_array(nhlt, 2))
+ printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");
+
+ /* 4 Channel DMIC array. */
+ if (nhlt_soc_add_dmic_array(nhlt, 4))
+ printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n");
+
+ /* Maxim MAX98927 Smart Amps for left and right channel */
+ if (nhlt_soc_add_max98927(nhlt, AUDIO_LINK_SSP0))
+ printk(BIOS_ERR, "Couldn't add Maxim MAX98927\n");
+
+ /* Realtek RT5663 Headset codec. */
+ if (nhlt_soc_add_rt5663(nhlt, AUDIO_LINK_SSP1))
+ printk(BIOS_ERR, "Couldn't add Realtek RT5663.\n");
+}
+
+void __weak variant_nhlt_oem_overrides(const char **oem_id,
+ const char **oem_table_id,
+ uint32_t *oem_revision)
+{
+ *oem_id = "GOOGLE";
+ *oem_table_id = "RAMMUSMAX";
+ *oem_revision = 0;
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I169c225e28183a7a93f1142a3bf87a60b26ce9ca
Gerrit-Change-Number: 27547
Gerrit-PatchSet: 1
Gerrit-Owner: Zhuohao Lee <zhuohao at chromium.org>
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