[coreboot-gerrit] Change in coreboot[master]: riscv: update src/arch/riscv/bootblock.S

[Xiang Wang (Code Review)]

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/27545


Change subject: riscv: update src/arch/riscv/bootblock.S
......................................................................

riscv: update src/arch/riscv/bootblock.S

Save the FDT pointer to memory. Make mscratch vacate for exception context switching.

Change-Id: I24554528969e36c9e98c0ebd733e002e215a52e5
Signed-off-by: Xiang Wang <wxjstz at 126.com>
---
M src/arch/riscv/bootblock.S
1 file changed, 6 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/27545/1

diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
index 81a4455..f92ed4b 100644
--- a/src/arch/riscv/bootblock.S
+++ b/src/arch/riscv/bootblock.S
@@ -37,6 +37,12 @@
 	# initialize cache as ram
 	call cache_as_ram
 
+	# Save the FDT pointer to memory.
+	# Make mscratch vacate for exception context switching.
+	csrrw a1, mscratch, zero
+	la    t0, rom_fdt
+	sd    a1, 0(t0)
+
 	# initialize stack point for each hart
 	# and the stack must be page-aligned.
 	# 0xDEADBEEF used to check stack overflow

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I24554528969e36c9e98c0ebd733e002e215a52e5
Gerrit-Change-Number: 27545
Gerrit-PatchSet: 1
Gerrit-Owner: Xiang Wang <wxjstz at 126.com>
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