[coreboot-gerrit] Change in coreboot[master]: arch/riscv: Fix makefile to only set flags for riscv

[Martin Roth (Code Review)]

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/27535


Change subject: arch/riscv: Fix makefile to only set flags for riscv
......................................................................

arch/riscv: Fix makefile to only set flags for riscv

This was updating flags for ALL architectures, not just riscv.
That was bad.

Change-Id: Ifa12ad98b04a5ac36148609ccdf46ca427fc5a27
Signed-off-by: Martin Roth <martin at coreboot.org>
---
M src/arch/riscv/Makefile.inc
1 file changed, 1 insertion(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/27535/1

diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 90e4240..a797076 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -21,7 +21,6 @@
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
 check-ramstage-overlap-regions += stack
-endif
 
 riscv_flags = -I$(src)/arch/riscv/ -mcmodel=$(CONFIG_RISCV_CODEMODEL) -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI)
 
@@ -32,6 +31,7 @@
 COMPILER_RT_romstage  = $(shell  $(GCC_romstage) $(riscv_flags) -print-libgcc-file-name)
 
 COMPILER_RT_ramstage  = $(shell  $(GCC_ramstage) $(riscv_flags) -print-libgcc-file-name)
+endif
 
 ################################################################################
 ## bootblock

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ifa12ad98b04a5ac36148609ccdf46ca427fc5a27
Gerrit-Change-Number: 27535
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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