[coreboot-gerrit] Change in coreboot[master]: mb/google/kahlee/variants/grunt: Select low-power mode for WiFi

[Simon Glass (Code Review)]

Simon Glass has uploaded this change for review. ( https://review.coreboot.org/27465


Change subject: mb/google/kahlee/variants/grunt: Select low-power mode for WiFi
......................................................................

mb/google/kahlee/variants/grunt: Select low-power mode for WiFi

Put the PCIe clock pins in power-saving mode for the WiFi module to save
power.

Note: This currently does not appear to have any effect on grunt.

BUG=b:110041917
BRANCH=none
TEST=boot without this patch:
$ iotools mem_read32 0xfed80e00
0x0046f3ff

With this patch:
$ iotools mem_read32 0xfed80e00
0x0046f3f1

Change-Id: I389815bc36b8610a30b0cbb9d73262ad392e0181
Signed-off-by: Simon Glass <sjg at chromium.org>
---
M src/mainboard/google/kahlee/mainboard.c
M src/soc/amd/stoneyridge/include/soc/southbridge.h
2 files changed, 10 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/27465/1

diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index cf600d2..a5a8dd1 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -150,6 +150,12 @@
 			GPP_CLK2_CLOCK_REQ_MAP_MASK,
 			GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 <<
 			GPP_CLK2_CLOCK_REQ_MAP_SHIFT);
+
+	/* Same for the WiFi */
+	clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),
+			GPP_CLK0_CLOCK_REQ_MAP_MASK,
+			GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 <<
+			GPP_CLK0_CLOCK_REQ_MAP_SHIFT);
 }
 
 /*************************************************
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 3127f5c..2e95309 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -366,6 +366,10 @@
 #define GPP_CLK2_CLOCK_REQ_MAP_MASK	(0xf << GPP_CLK2_CLOCK_REQ_MAP_SHIFT)
 #define GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2	3
 
+#define GPP_CLK0_CLOCK_REQ_MAP_SHIFT	0
+#define GPP_CLK0_CLOCK_REQ_MAP_MASK	(0xf << GPP_CLK0_CLOCK_REQ_MAP_SHIFT)
+#define GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0	1
+
 struct stoneyridge_aoac {
 	int enable;
 	int status;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I389815bc36b8610a30b0cbb9d73262ad392e0181
Gerrit-Change-Number: 27465
Gerrit-PatchSet: 1
Gerrit-Owner: Simon Glass <sjg at chromium.org>
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