[coreboot-gerrit] Change in coreboot[master]: riscv: add support for modifying compiler options

[Xiang Wang (Code Review)]

Hello build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/27442

to look at the new patch set (#3).

Change subject: riscv: add support for modifying compiler options
......................................................................

riscv: add support for modifying compiler options

Each HART of a SoC like fu540 supports a different ISA.
In order for the coreboot's code can run on each core, need to modify the
compile options. So add this code.

Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b
Signed-off-by: Xiang Wang <wxjstz at 126.com>
---
M src/arch/riscv/Kconfig
M src/arch/riscv/Makefile.inc
M src/soc/lowrisc/lowrisc/Kconfig
M src/soc/sifive/fu540/Kconfig
M src/soc/ucb/riscv/Kconfig
5 files changed, 50 insertions(+), 12 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/27442/3
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b
Gerrit-Change-Number: 27442
Gerrit-PatchSet: 3
Gerrit-Owner: Xiang Wang <wxjstz at 126.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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