[coreboot-gerrit] Change in coreboot[master]: uart/sifive: make divisor configurable

[Philipp Hug (Code Review)]

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/27440


Change subject: uart/sifive: make divisor configurable
......................................................................

uart/sifive: make divisor configurable

The SiFive UART on the HiFive Unleashed uses the tlclk as input clock
which runs at coreclk / 2.
The input frequency is configured in the board code depending on the
current stage. (bootblock + romstage run at 33.33Mhz, ramstage at 1Ghz)

Change-Id: Iaf66723dba3d308f809fde5b05dfc3e43f43bd42
---
M src/drivers/uart/sifive.c
M src/soc/sifive/fu540/Kconfig
M src/soc/sifive/fu540/uart.c
3 files changed, 20 insertions(+), 5 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/27440/1

diff --git a/src/drivers/uart/sifive.c b/src/drivers/uart/sifive.c
index dd47caf..ce8ead0 100644
--- a/src/drivers/uart/sifive.c
+++ b/src/drivers/uart/sifive.c
@@ -46,11 +46,10 @@
 #define IP_TXWM			BIT(0)
 #define IP_RXWM			BIT(1)
 
-void uart_init(int idx)
+static void sifive_uart_init(struct sifive_uart_registers *regs, int div)
 {
-	struct sifive_uart_registers *regs = uart_platform_baseptr(idx);
-
-	/* TODO: Configure the divisor */
+	/* Configure the divisor */
+	write32(&regs->div, div);
 
 	/* Enable transmission, one stop bit, transmit watermark at 1 */
 	write32(&regs->txctrl, TXCTRL_TXEN|TXCTRL_NSTOP(1)|TXCTRL_TXCNT(1));
@@ -59,6 +58,14 @@
 	write32(&regs->rxctrl, RXCTRL_RXEN|RXCTRL_RXCNT(0));
 }
 
+void uart_init(int idx)
+{
+	unsigned int div;
+	div = uart_baudrate_divisor(get_uart_baudrate(),
+		uart_platform_refclk(), uart_input_clock_divider());
+	sifive_uart_init(uart_platform_baseptr(idx), div);
+}
+
 static bool uart_can_tx(struct sifive_uart_registers *regs)
 {
 	return !(read32(&regs->txdata) & TXDATA_FULL);
diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig
index d247c28..df9a278 100644
--- a/src/soc/sifive/fu540/Kconfig
+++ b/src/soc/sifive/fu540/Kconfig
@@ -20,7 +20,7 @@
 	select ARCH_RAMSTAGE_RISCV
 	select BOOTBLOCK_CONSOLE
 	select DRIVERS_UART_SIFIVE
-
+	select UART_OVERRIDE_REFCLK
 if SOC_SIFIVE_FU540
 
 endif
diff --git a/src/soc/sifive/fu540/uart.c b/src/soc/sifive/fu540/uart.c
index 940dc97..b9dc7df 100644
--- a/src/soc/sifive/fu540/uart.c
+++ b/src/soc/sifive/fu540/uart.c
@@ -23,3 +23,11 @@
 	else
 		return 0;
 }
+
+unsigned int uart_platform_refclk(void)
+{
+	/*
+	 * The SiFive UART uses tlclk, which is coreclk/2 as input
+         */
+        return 33330000 / 2;
+}

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iaf66723dba3d308f809fde5b05dfc3e43f43bd42
Gerrit-Change-Number: 27440
Gerrit-PatchSet: 1
Gerrit-Owner: Philipp Hug <philipp at hug.cx>
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