[coreboot-gerrit] Change in coreboot[master]: riscv: src/arch/riscv/bootblock.S
Xiang Wang (Code Review)
gerrit at coreboot.org
Wed Jul 11 06:17:23 CEST 2018
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/27430
to look at the new patch set (#3).
Change subject: riscv: src/arch/riscv/bootblock.S
......................................................................
riscv: src/arch/riscv/bootblock.S
Add an interface to support cache as ram.
Initialize stack pointer for each hart.
Change-Id: Ic3920e01dd1a7f047a53de57250589000a111409
Signed-off-by: Xiang Wang <wxjstz at 126.com>
---
M src/arch/riscv/bootblock.S
1 file changed, 21 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/27430/3
--
To view, visit https://review.coreboot.org/27430
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ic3920e01dd1a7f047a53de57250589000a111409
Gerrit-Change-Number: 27430
Gerrit-PatchSet: 3
Gerrit-Owner: Xiang Wang <wxjstz at 126.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180711/864e9e2f/attachment.html>
More information about the coreboot-gerrit
mailing list