[coreboot-gerrit] Change in coreboot[master]: mediatek/mt8183: Add GPIO support
Tristan Hsieh (Code Review)
gerrit at coreboot.org
Mon Jul 9 13:25:10 CEST 2018
Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/27417
Change subject: mediatek/mt8183: Add GPIO support
......................................................................
mediatek/mt8183: Add GPIO support
This patch implements gpio_set_pull() and gpio_set_mode() to support IO
config for other drivers (ex. SPI), and links the common mediatek GPIO
code to implement the requested functions in src/include/gpio.h.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui.
Change-Id: Ia2b0d88e9b70c9ad148797d77dc9e79ce1bcb64a
Signed-off-by: jg_poxu <jg_poxu at mediatek.com>
---
M src/soc/mediatek/mt8183/Makefile.inc
A src/soc/mediatek/mt8183/gpio.c
M src/soc/mediatek/mt8183/include/soc/addressmap.h
A src/soc/mediatek/mt8183/include/soc/gpio.h
A src/soc/mediatek/mt8183/include/soc/pinmux.h
5 files changed, 555 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/27417/1
diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc
index 74b0ae8..b99664f 100644
--- a/src/soc/mediatek/mt8183/Makefile.inc
+++ b/src/soc/mediatek/mt8183/Makefile.inc
@@ -1,6 +1,7 @@
ifeq ($(CONFIG_SOC_MEDIATEK_MT8183),y)
bootblock-y += bootblock.c
+bootblock-y += ../common/gpio.c gpio.c
bootblock-$(CONFIG_SPI_FLASH) += spi.c
bootblock-y += ../common/timer.c
ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
@@ -8,17 +9,20 @@
endif
bootblock-y += ../common/wdt.c
+verstage-y += ../common/gpio.c gpio.c
verstage-$(CONFIG_SPI_FLASH) += spi.c
verstage-y += ../common/timer.c
verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
verstage-y += ../common/wdt.c
+romstage-y += ../common/gpio.c gpio.c
romstage-$(CONFIG_SPI_FLASH) += spi.c
romstage-y += ../common/timer.c
romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
romstage-y += ../common/wdt.c
ramstage-y += ../common/cbmem.c emi.c
+ramstage-y += ../common/gpio.c gpio.c
ramstage-y += ../common/mtcmos.c mtcmos.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c
ramstage-y += ../common/timer.c
diff --git a/src/soc/mediatek/mt8183/gpio.c b/src/soc/mediatek/mt8183/gpio.c
new file mode 100644
index 0000000..cdb8e32
--- /dev/null
+++ b/src/soc/mediatek/mt8183/gpio.c
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <gpio.h>
+
+enum {
+ EN_OFFSET = 0x60,
+ SEL_OFFSET = 0x80,
+};
+
+static void gpio_set_pull_pupd(gpio_t gpio, enum pull_enable enable,
+ enum pull_select select)
+{
+ void *reg = GPIO_GET_BASE(gpio) + GPIO_GET_OFFSET(gpio);
+ int bit = GPIO_GET_BIT(gpio);
+
+ if (enable == GPIO_PULL_ENABLE) {
+ if (select == GPIO_PULL_DOWN)
+ setbits_le32(reg, 1 << (bit + 2));
+ else
+ clrbits_le32(reg, 1 << (bit + 2));
+ }
+
+ if (enable == GPIO_PULL_ENABLE)
+ clrsetbits_le32(reg, 1 << (bit + 1), 1 << bit);
+ else
+ clrbits_le32(reg, 3 << bit);
+}
+
+static void gpio_set_pull_en_sel(gpio_t gpio, enum pull_enable enable,
+ enum pull_select select)
+{
+ void *reg = GPIO_GET_BASE(gpio) + GPIO_GET_OFFSET(gpio);
+ int bit = GPIO_GET_BIT(gpio);
+
+ if (enable == GPIO_PULL_ENABLE) {
+ if (select == GPIO_PULL_DOWN)
+ clrbits_le32(reg + SEL_OFFSET, 1 << bit);
+ else
+ setbits_le32(reg + SEL_OFFSET, 1 << bit);
+ }
+
+ if (enable == GPIO_PULL_ENABLE)
+ setbits_le32(reg + EN_OFFSET, 1 << bit);
+ else
+ clrbits_le32(reg + EN_OFFSET, 1 << bit);
+}
+
+void gpio_set_pull(gpio_t gpio, enum pull_enable enable,
+ enum pull_select select)
+{
+ if (GPIO_GET_FLAG(gpio))
+ gpio_set_pull_pupd(gpio, enable, select);
+ else
+ gpio_set_pull_en_sel(gpio, enable, select);
+}
diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h
index a0d7f1c..f29931c 100644
--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h
@@ -23,10 +23,19 @@
enum {
INFRACFG_AO_BASE = IO_PHYS + 0x00001000,
+ GPIO_BASE = IO_PHYS + 0x00005000,
SPM_BASE = IO_PHYS + 0x00006000,
RGU_BASE = IO_PHYS + 0x00007000,
GPT_BASE = IO_PHYS + 0x00008000,
UART0_BASE = IO_PHYS + 0x01002000,
+ IOCFG_RT_BASE = IO_PHYS + 0x01C50000,
+ IOCFG_RM_BASE = IO_PHYS + 0x01D20000,
+ IOCFG_RB_BASE = IO_PHYS + 0x01D30000,
+ IOCFG_LB_BASE = IO_PHYS + 0x01E70000,
+ IOCFG_LM_BASE = IO_PHYS + 0x01E80000,
+ IOCFG_BL_BASE = IO_PHYS + 0x01E90000,
+ IOCFG_LT_BASE = IO_PHYS + 0x01F20000,
+ IOCFG_TL_BASE = IO_PHYS + 0x01F30000,
SMI_BASE = IO_PHYS + 0x04019000,
};
diff --git a/src/soc/mediatek/mt8183/include/soc/gpio.h b/src/soc/mediatek/mt8183/include/soc/gpio.h
new file mode 100644
index 0000000..9897ee0
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/gpio.h
@@ -0,0 +1,260 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_MEDIATEK_MT8183_GPIO_H
+#define SOC_MEDIATEK_MT8183_GPIO_H
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+enum {
+ MAX_GPIO_REG_BITS = 32,
+ MAX_GPIO_MODE_PER_REG = 8,
+ GPIO_MODE_BITS = 4,
+};
+
+enum pull_enable {
+ GPIO_PULL_DISABLE = 0,
+ GPIO_PULL_ENABLE = 1,
+};
+
+enum pull_select {
+ GPIO_PULL_DOWN = 0,
+ GPIO_PULL_UP = 1,
+};
+
+#define IOCFG_TO_GPIO_BASE(x) ((x >> 16) & 0xff)
+#define GPIO_TO_IOCFG_BASE(x) ((void *)0x11000000 + ((x & 0xff) << 16))
+
+#define GPIO(id, flag, bit, base, offset) \
+ (((id & 0xff) << 0) | \
+ ((flag & 0x7) << 8) | \
+ ((bit & 0x1f) << 11) | \
+ ((IOCFG_TO_GPIO_BASE(base) & 0xff) << 16) | \
+ ((offset & 0xff) << 24))
+
+#define GPIO_GET_ID(x) ((x >> 0) & 0xff)
+#define GPIO_GET_FLAG(x) ((x >> 8) & 0x7)
+#define GPIO_GET_BIT(x) ((x >> 11) & 0x1f)
+#define GPIO_GET_BASE(x) (GPIO_TO_IOCFG_BASE((x >> 16) & 0xff))
+#define GPIO_GET_OFFSET(x) ((x >> 24) & 0xff)
+
+typedef enum {
+ GPIO_PAD_0 = GPIO(0, 0, 6, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_1 = GPIO(1, 0, 7, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_2 = GPIO(2, 0, 8, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_3 = GPIO(3, 0, 9, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_4 = GPIO(4, 0, 11, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_5 = GPIO(5, 0, 12, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_6 = GPIO(6, 0, 13, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_7 = GPIO(7, 0, 14, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_8 = GPIO(8, 0, 0, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_9 = GPIO(9, 0, 26, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_10 = GPIO(10, 0, 27, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_11 = GPIO(11, 0, 10, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_12 = GPIO(12, 0, 17, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_13 = GPIO(13, 0, 6, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_14 = GPIO(14, 0, 7, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_15 = GPIO(15, 0, 8, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_16 = GPIO(16, 0, 9, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_17 = GPIO(17, 0, 10, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_18 = GPIO(18, 0, 11, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_19 = GPIO(19, 0, 12, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_20 = GPIO(20, 0, 13, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_21 = GPIO(21, 0, 14, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_22 = GPIO(22, 0, 15, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_23 = GPIO(23, 0, 16, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_24 = GPIO(24, 0, 17, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_25 = GPIO(25, 0, 18, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_26 = GPIO(26, 0, 19, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_27 = GPIO(27, 0, 20, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_28 = GPIO(28, 0, 21, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_29 = GPIO(29, 1, 0, IOCFG_LM_BASE, 0xc0),
+ GPIO_PAD_30 = GPIO(30, 1, 4, IOCFG_LM_BASE, 0xc0),
+ GPIO_PAD_31 = GPIO(31, 1, 8, IOCFG_LM_BASE, 0xc0),
+ GPIO_PAD_32 = GPIO(32, 1, 12, IOCFG_LM_BASE, 0xc0),
+ GPIO_PAD_33 = GPIO(33, 1, 16, IOCFG_LM_BASE, 0xc0),
+ GPIO_PAD_34 = GPIO(34, 1, 20, IOCFG_LM_BASE, 0xc0),
+ GPIO_PAD_35 = GPIO(35, 1, 0, IOCFG_LB_BASE, 0xc0),
+ GPIO_PAD_36 = GPIO(36, 1, 4, IOCFG_LB_BASE, 0xc0),
+ GPIO_PAD_37 = GPIO(37, 1, 8, IOCFG_LB_BASE, 0xc0),
+ GPIO_PAD_38 = GPIO(38, 1, 12, IOCFG_LB_BASE, 0xc0),
+ GPIO_PAD_39 = GPIO(39, 1, 16, IOCFG_LB_BASE, 0xc0),
+ GPIO_PAD_40 = GPIO(40, 1, 20, IOCFG_LB_BASE, 0xc0),
+ GPIO_PAD_41 = GPIO(41, 1, 24, IOCFG_LB_BASE, 0xc0),
+ GPIO_PAD_42 = GPIO(42, 1, 28, IOCFG_LB_BASE, 0xc0),
+ GPIO_PAD_43 = GPIO(43, 0, 8, IOCFG_LB_BASE, 0x00),
+ GPIO_PAD_44 = GPIO(44, 0, 9, IOCFG_LB_BASE, 0x00),
+ GPIO_PAD_45 = GPIO(45, 0, 10, IOCFG_LB_BASE, 0x00),
+ GPIO_PAD_46 = GPIO(46, 0, 11, IOCFG_LB_BASE, 0x00),
+ GPIO_PAD_47 = GPIO(47, 0, 12, IOCFG_LB_BASE, 0x00),
+ GPIO_PAD_48 = GPIO(48, 0, 13, IOCFG_LB_BASE, 0x00),
+ GPIO_PAD_49 = GPIO(49, 0, 14, IOCFG_LB_BASE, 0x00),
+ GPIO_PAD_50 = GPIO(50, 0, 0, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_51 = GPIO(51, 0, 1, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_52 = GPIO(52, 0, 2, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_53 = GPIO(53, 0, 3, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_54 = GPIO(54, 0, 4, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_55 = GPIO(55, 0, 5, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_56 = GPIO(56, 0, 6, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_57 = GPIO(57, 0, 7, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_58 = GPIO(58, 0, 8, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_59 = GPIO(59, 0, 9, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_60 = GPIO(60, 0, 10, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_61 = GPIO(61, 0, 0, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_62 = GPIO(62, 0, 1, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_63 = GPIO(63, 0, 2, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_64 = GPIO(64, 0, 3, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_65 = GPIO(65, 0, 4, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_66 = GPIO(66, 0, 5, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_67 = GPIO(67, 0, 6, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_68 = GPIO(68, 0, 7, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_69 = GPIO(69, 0, 8, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_70 = GPIO(70, 0, 9, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_71 = GPIO(71, 0, 10, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_72 = GPIO(72, 0, 11, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_73 = GPIO(73, 0, 12, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_74 = GPIO(74, 0, 13, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_75 = GPIO(75, 0, 14, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_76 = GPIO(76, 0, 15, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_77 = GPIO(77, 0, 16, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_78 = GPIO(78, 0, 17, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_79 = GPIO(79, 0, 18, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_80 = GPIO(80, 0, 19, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_81 = GPIO(81, 0, 20, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_82 = GPIO(82, 0, 21, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_83 = GPIO(83, 0, 22, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_84 = GPIO(84, 0, 23, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_85 = GPIO(85, 0, 24, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_86 = GPIO(86, 0, 25, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_87 = GPIO(87, 0, 26, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_88 = GPIO(88, 0, 27, IOCFG_RB_BASE, 0x00),
+ GPIO_PAD_89 = GPIO(89, 0, 24, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_90 = GPIO(90, 0, 1, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_91 = GPIO(91, 1, 0, IOCFG_RM_BASE, 0xc0),
+ GPIO_PAD_92 = GPIO(92, 1, 4, IOCFG_RM_BASE, 0xc0),
+ GPIO_PAD_93 = GPIO(93, 1, 8, IOCFG_RM_BASE, 0xc0),
+ GPIO_PAD_94 = GPIO(94, 1, 12, IOCFG_RM_BASE, 0xc0),
+ GPIO_PAD_95 = GPIO(95, 0, 15, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_96 = GPIO(96, 0, 17, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_97 = GPIO(97, 0, 18, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_98 = GPIO(98, 0, 19, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_99 = GPIO(99, 0, 20, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_100 = GPIO(100, 0, 21, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_101 = GPIO(101, 0, 22, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_102 = GPIO(102, 0, 23, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_103 = GPIO(103, 0, 28, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_104 = GPIO(104, 0, 29, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_105 = GPIO(105, 0, 30, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_106 = GPIO(106, 0, 31, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_107 = GPIO(107, 0, 0, IOCFG_RT_BASE, 0x00),
+ GPIO_PAD_108 = GPIO(108, 0, 1, IOCFG_RT_BASE, 0x00),
+ GPIO_PAD_109 = GPIO(109, 0, 2, IOCFG_RT_BASE, 0x00),
+ GPIO_PAD_110 = GPIO(110, 0, 3, IOCFG_RT_BASE, 0x00),
+ GPIO_PAD_111 = GPIO(111, 0, 4, IOCFG_RT_BASE, 0x00),
+ GPIO_PAD_112 = GPIO(112, 0, 5, IOCFG_RT_BASE, 0x00),
+ GPIO_PAD_113 = GPIO(113, 0, 6, IOCFG_RT_BASE, 0x00),
+ GPIO_PAD_114 = GPIO(114, 0, 7, IOCFG_RT_BASE, 0x00),
+ GPIO_PAD_115 = GPIO(115, 0, 8, IOCFG_RT_BASE, 0x00),
+ GPIO_PAD_116 = GPIO(116, 0, 9, IOCFG_RT_BASE, 0x00),
+ GPIO_PAD_117 = GPIO(117, 0, 10, IOCFG_RT_BASE, 0x00),
+ GPIO_PAD_118 = GPIO(118, 0, 11, IOCFG_RT_BASE, 0x00),
+ GPIO_PAD_119 = GPIO(119, 0, 12, IOCFG_RT_BASE, 0x00),
+ GPIO_PAD_120 = GPIO(120, 0, 13, IOCFG_RT_BASE, 0x00),
+ GPIO_PAD_121 = GPIO(121, 0, 14, IOCFG_RT_BASE, 0x00),
+ GPIO_PAD_122 = GPIO(122, 1, 0, IOCFG_TL_BASE, 0xc0),
+ GPIO_PAD_123 = GPIO(123, 1, 4, IOCFG_TL_BASE, 0xc0),
+ GPIO_PAD_124 = GPIO(124, 1, 8, IOCFG_TL_BASE, 0xc0),
+ GPIO_PAD_125 = GPIO(125, 1, 12, IOCFG_TL_BASE, 0xc0),
+ GPIO_PAD_126 = GPIO(126, 1, 16, IOCFG_TL_BASE, 0xc0),
+ GPIO_PAD_127 = GPIO(127, 1, 20, IOCFG_TL_BASE, 0xc0),
+ GPIO_PAD_128 = GPIO(128, 1, 24, IOCFG_TL_BASE, 0xc0),
+ GPIO_PAD_129 = GPIO(129, 1, 28, IOCFG_TL_BASE, 0xc0),
+ GPIO_PAD_130 = GPIO(130, 1, 0, IOCFG_TL_BASE, 0xd0),
+ GPIO_PAD_131 = GPIO(131, 1, 4, IOCFG_TL_BASE, 0xd0),
+ GPIO_PAD_132 = GPIO(132, 1, 8, IOCFG_TL_BASE, 0xd0),
+ GPIO_PAD_133 = GPIO(133, 1, 12, IOCFG_TL_BASE, 0xd0),
+ GPIO_PAD_134 = GPIO(134, 0, 0, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_135 = GPIO(135, 0, 1, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_136 = GPIO(136, 0, 2, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_137 = GPIO(137, 0, 3, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_138 = GPIO(138, 0, 4, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_139 = GPIO(139, 0, 5, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_140 = GPIO(140, 0, 6, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_141 = GPIO(141, 0, 7, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_142 = GPIO(142, 0, 8, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_143 = GPIO(143, 0, 9, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_144 = GPIO(144, 0, 11, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_145 = GPIO(145, 0, 12, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_146 = GPIO(146, 0, 13, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_147 = GPIO(147, 0, 14, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_148 = GPIO(148, 0, 15, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_149 = GPIO(149, 0, 16, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_150 = GPIO(150, 0, 18, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_151 = GPIO(151, 0, 19, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_152 = GPIO(152, 0, 20, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_153 = GPIO(153, 0, 21, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_154 = GPIO(154, 0, 22, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_155 = GPIO(155, 0, 23, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_156 = GPIO(156, 0, 24, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_157 = GPIO(157, 0, 25, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_158 = GPIO(158, 0, 26, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_159 = GPIO(159, 0, 27, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_160 = GPIO(160, 0, 28, IOCFG_LT_BASE, 0x00),
+ GPIO_PAD_161 = GPIO(161, 0, 0, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_162 = GPIO(162, 0, 1, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_163 = GPIO(163, 0, 2, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_164 = GPIO(164, 0, 3, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_165 = GPIO(165, 0, 4, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_166 = GPIO(166, 0, 5, IOCFG_LM_BASE, 0x00),
+ GPIO_PAD_167 = GPIO(167, 0, 11, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_168 = GPIO(168, 0, 12, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_169 = GPIO(169, 0, 13, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_170 = GPIO(170, 0, 14, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_171 = GPIO(171, 0, 15, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_172 = GPIO(172, 0, 16, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_173 = GPIO(173, 0, 17, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_174 = GPIO(174, 0, 18, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_175 = GPIO(175, 0, 19, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_176 = GPIO(176, 0, 20, IOCFG_BL_BASE, 0x00),
+ GPIO_PAD_177 = GPIO(177, 0, 10, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_178 = GPIO(178, 0, 16, IOCFG_RM_BASE, 0x00),
+ GPIO_PAD_179 = GPIO(179, 0, 25, IOCFG_RM_BASE, 0x00),
+} gpio_t;
+
+struct val_regs {
+ uint32_t val;
+ uint32_t set;
+ uint32_t rst;
+ uint32_t align;
+};
+
+struct gpio_regs {
+ struct val_regs dir[6];
+ uint8_t rsv00[160];
+ struct val_regs dout[6];
+ uint8_t rsv01[160];
+ struct val_regs din[6];
+ uint8_t rsv02[160];
+ struct val_regs mode[23];
+};
+
+static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE);
+
+void gpio_set_pull(gpio_t gpio, enum pull_enable enable,
+ enum pull_select select);
+void gpio_set_mode(gpio_t gpio, int mode);
+
+#endif
diff --git a/src/soc/mediatek/mt8183/include/soc/pinmux.h b/src/soc/mediatek/mt8183/include/soc/pinmux.h
new file mode 100644
index 0000000..56b3fe9
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/pinmux.h
@@ -0,0 +1,213 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef SOC_MEDIATEK_MT8183_PINMUX_H
+#define SOC_MEDIATEK_MT8183_PINMUX_H
+
+#include <soc/gpio.h>
+
+#define PINMUX_CONSTANTS(index, name, func1, func2, func3, func4, func5, func6, func7) \
+ name = index, \
+ name##_FUNC_##func1 = 1, \
+ name##_FUNC_##func2 = 2, \
+ name##_FUNC_##func3 = 3, \
+ name##_FUNC_##func4 = 4, \
+ name##_FUNC_##func5 = 5, \
+ name##_FUNC_##func6 = 6, \
+ name##_FUNC_##func7 = 7
+
+enum {
+ PINMUX_CONSTANTS(GPIO_PAD_0, PAD_EINT0, MRG_SYNC, PCM0_SYNC, TP_GPIO0_AO, SRCLKENAI0, SCP_SPI2_CS, I2S3_MCK, SPI2_CSB),
+ PINMUX_CONSTANTS(GPIO_PAD_1, PAD_EINT1, MRG_CLK, PCM0_CLK, TP_GPIO1_AO, CLKM3, SCP_SPI2_MO, I2S3_BCK, SPI2_MO),
+ PINMUX_CONSTANTS(GPIO_PAD_2, PAD_EINT2, MRG_DO, PCM0_DO, TP_GPIO2_AO, SCL6, SCP_SPI2_CK, I2S3_LRCK, SPI2_CLK),
+ PINMUX_CONSTANTS(GPIO_PAD_3, PAD_EINT3, MRG_DI, PCM0_DI, TP_GPIO3_AO, SDA6, TDM_MCK, I2S3_DO, SCP_VREQ_VAO),
+ PINMUX_CONSTANTS(GPIO_PAD_4, PAD_EINT4, PWM_B, I2S0_MCK, SSPM_UTXD_AO, MD_URXD1, TDM_BCK, TP_GPIO4_AO, DAP_MD32_SWD),
+ PINMUX_CONSTANTS(GPIO_PAD_5, PAD_EINT5, PWM_C, I2S0_BCK, SSPM_URXD_AO, MD_UTXD1, TDM_LRCK, TP_GPIO5_AO, DAP_MD32_SWCK),
+ PINMUX_CONSTANTS(GPIO_PAD_6, PAD_EINT6, PWM_A, I2S0_LRCK, IDDIG, MD_URXD0, TDM_DATA0, TP_GPIO6_AO, CMFLASH),
+ PINMUX_CONSTANTS(GPIO_PAD_7, PAD_EINT7, SPI1_B_MI, I2S0_DI, USB_DRVVBUS, MD_UTXD0, TDM_DATA1, TP_GPIO7_AO, DVFSRC_EXT_REQ),
+ PINMUX_CONSTANTS(GPIO_PAD_8, PAD_EINT8, SPI1_B_CSB, ANT_SEL3, SCL7, CONN_MCU_TRST_B, TDM_DATA2, MD_INT0, JTRSTN_SEL1),
+ PINMUX_CONSTANTS(GPIO_PAD_9, PAD_EINT9, SPI1_B_MO, ANT_SEL4, CMMCLK2, CONN_MCU_DBGACK_N, SSPM_JTAG_TRSTN, IO_JTAG_TRSTN, DBG_MON_B10),
+ PINMUX_CONSTANTS(GPIO_PAD_10, PAD_EINT10, SPI1_B_CLK, ANT_SEL5, CMMCLK3, CONN_MCU_DBGI_N, TDM_DATA3, EXT_FRAME_SYNC, DBG_MON_B11),
+ PINMUX_CONSTANTS(GPIO_PAD_11, PAD_SCL6, TP_URXD1_AO, IDDIG, SCL6, UCTS1, UCTS0, SRCLKENAI1, I2S5_MCK),
+ PINMUX_CONSTANTS(GPIO_PAD_12, PAD_SDA6, TP_UTXD1_AO, USB_DRVVBUS, SDA6, URTS1, URTS0, I2S2_DI2, I2S5_BCK),
+ PINMUX_CONSTANTS(GPIO_PAD_13, PAD_DPI_D0, DBPI_D0, SPI5_MI, PCM0_SYNC, MD_URXD0, ANT_SEL3, I2S0_MCK, DBG_MON_B15),
+ PINMUX_CONSTANTS(GPIO_PAD_14, PAD_DPI_D1, DBPI_D1, SPI5_CSB, PCM0_CLK, MD_UTXD0, ANT_SEL4, I2S0_BCK, DBG_MON_B16),
+ PINMUX_CONSTANTS(GPIO_PAD_15, PAD_DPI_D2, DBPI_D2, SPI5_MO, PCM0_DO, MD_URXD1, ANT_SEL5, I2S0_LRCK, DBG_MON_B17),
+ PINMUX_CONSTANTS(GPIO_PAD_16, PAD_DPI_D3, DBPI_D3, SPI5_CLK, PCM0_DI, MD_UTXD1, ANT_SEL6, I2S0_DI, DBG_MON_B23),
+ PINMUX_CONSTANTS(GPIO_PAD_17, PAD_DPI_D4, DBPI_D4, SPI4_MI, CONN_MCU_TRST_B, MD_INT0, ANT_SEL7, I2S3_MCK, DBG_MON_A1),
+ PINMUX_CONSTANTS(GPIO_PAD_18, PAD_DPI_D5, DBPI_D5, SPI4_CSB, CONN_MCU_DBGI_N, MD_INT0, SCP_VREQ_VAO, I2S3_BCK, DBG_MON_A2),
+ PINMUX_CONSTANTS(GPIO_PAD_19, PAD_DPI_D6, DBPI_D6, SPI4_MO, CONN_MCU_TDO, MD_INT2_C2K_UIM1_HOT_PLUG, URXD1, I2S3_LRCK, DBG_MON_A3),
+ PINMUX_CONSTANTS(GPIO_PAD_20, PAD_DPI_D7, DBPI_D7, SPI4_CLK, CONN_MCU_DBGACK_N, MD_INT1_C2K_UIM0_HOT_PLUG, UTXD1, I2S3_DO, DBG_MON_A19),
+ PINMUX_CONSTANTS(GPIO_PAD_21, PAD_DPI_D8, DBPI_D8, SPI3_MI, CONN_MCU_TMS, DAP_MD32_SWD, CONN_MCU_AICE_TMSC, I2S2_MCK, DBG_MON_B5),
+ PINMUX_CONSTANTS(GPIO_PAD_22, PAD_DPI_D9, DBPI_D9, SPI3_CSB, CONN_MCU_TCK, DAP_MD32_SWCK, CONN_MCU_AICE_TCKC, I2S2_BCK, DBG_MON_B6),
+ PINMUX_CONSTANTS(GPIO_PAD_23, PAD_DPI_D10, DBPI_D10, SPI3_MO, CONN_MCU_TDI, UCTS1, EXT_FRAME_SYNC, I2S2_LRCK, DBG_MON_B7),
+ PINMUX_CONSTANTS(GPIO_PAD_24, PAD_DPI_D11, DBPI_D11, SPI3_CLK, SRCLKENAI0, URTS1, IO_JTAG_TCK, I2S2_DI, DBG_MON_B31),
+ PINMUX_CONSTANTS(GPIO_PAD_25, PAD_DPI_HSYNC, DBPI_HSYNC, ANT_SEL0, SCL6, KPCOL2, IO_JTAG_TMS, I2S1_MCK, DBG_MON_B0),
+ PINMUX_CONSTANTS(GPIO_PAD_26, PAD_DPI_VSYNC, DBPI_VSYNC, ANT_SEL1, SDA6, KPROW2, IO_JTAG_TDI, I2S1_BCK, DBG_MON_B1),
+ PINMUX_CONSTANTS(GPIO_PAD_27, PAD_DPI_DE, DBPI_DE, ANT_SEL2, SCL7, DMIC_CLK, IO_JTAG_TDO, I2S1_LRCK, DBG_MON_B9),
+ PINMUX_CONSTANTS(GPIO_PAD_28, PAD_DPI_CK, DBPI_CK, DVFSRC_EXT_REQ, SDA7, DMIC_DAT, IO_JTAG_TRSTN, I2S1_DO, DBG_MON_B32),
+ PINMUX_CONSTANTS(GPIO_PAD_29, PAD_MSDC1_CLK, MSDC1_CLK, IO_JTAG_TCK, UDI_TCK, CONN_DSP_JCK, SSPM_JTAG_TCK, PCM1_CLK, DBG_MON_A6),
+ PINMUX_CONSTANTS(GPIO_PAD_30, PAD_MSDC1_DAT3, MSDC1_DAT3, DAP_MD32_SWD, CONN_MCU_AICE_TMSC, CONN_DSP_JINTP, SSPM_JTAG_TRSTN, PCM1_DI, DBG_MON_A7),
+ PINMUX_CONSTANTS(GPIO_PAD_31, PAD_MSDC1_CMD, MSDC1_CMD, IO_JTAG_TMS, UDI_TMS, CONN_DSP_JMS, SSPM_JTAG_TMS, PCM1_SYNC, DBG_MON_A8),
+ PINMUX_CONSTANTS(GPIO_PAD_32, PAD_MSDC1_DAT0, MSDC1_DAT0, IO_JTAG_TDI, UDI_TDI, CONN_DSP_JDI, SSPM_JTAG_TDI, PCM1_DO0, DBG_MON_A9),
+ PINMUX_CONSTANTS(GPIO_PAD_33, PAD_MSDC1_DAT2, MSDC1_DAT2, IO_JTAG_TRSTN, UDI_NTRST, DAP_MD32_SWCK, CONN_MCU_AICE_TCKC, PCM1_DO2, DBG_MON_A10),
+ PINMUX_CONSTANTS(GPIO_PAD_34, PAD_MSDC1_DAT1, MSDC1_DAT1, IO_JTAG_TDO, UDI_TDO, CONN_DSP_JDO, SSPM_JTAG_TDO, PCM1_DO1, DBG_MON_A11),
+ PINMUX_CONSTANTS(GPIO_PAD_35, PAD_SIM2_SIO, MD1_SIM2_SIO, CCU_JTAG_TDO, MD1_SIM1_SIO, RES4, SCP_JTAG_TDO, CONN_DSP_JMS, DBG_MON_A28),
+ PINMUX_CONSTANTS(GPIO_PAD_36, PAD_SIM2_SRST, MD1_SIM2_SRST, CCU_JTAG_TMS, MD1_SIM1_SRST, CONN_MCU_AICE_TMSC, SCP_JTAG_TMS, CONN_DSP_JINTP, DBG_MON_A29),
+ PINMUX_CONSTANTS(GPIO_PAD_37, PAD_SIM2_SCLK, MD1_SIM2_SCLK, CCU_JTAG_TDI, MD1_SIM1_SCLK, RES4, SCP_JTAG_TDI, CONN_DSP_JDO, DBG_MON_A30),
+ PINMUX_CONSTANTS(GPIO_PAD_38, PAD_SIM1_SCLK, MD1_SIM1_SCLK, RES2, MD1_SIM2_SCLK, CONN_MCU_AICE_TCKC, RES5, RES6, DBG_MON_A20),
+ PINMUX_CONSTANTS(GPIO_PAD_39, PAD_SIM1_SRST, MD1_SIM1_SRST, CCU_JTAG_TCK, MD1_SIM2_SRST, RES4, SCP_JTAG_TCK, CONN_DSP_JCK, DBG_MON_A31),
+ PINMUX_CONSTANTS(GPIO_PAD_40, PAD_SIM1_SIO, MD1_SIM1_SIO, CCU_JTAG_TRST, MD1_SIM2_SIO, RES4, SCP_JTAG_TRSTN, CONN_DSP_JDI, DBG_MON_A32),
+ PINMUX_CONSTANTS(GPIO_PAD_41, PAD_IDDIG, IDDIG, URXD1, UCTS0, SSPM_UTXD_AO, EXT_FRAME_SYNC, DMIC_CLK, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_42, PAD_DRVBUS, USB_DRVVBUS, UTXD1, URTS0, SSPM_URXD_AO, EXT_FRAME_SYNC, DMIC_DAT, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_43, PAD_DISP_PWM, DISP_PWM, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_44, PAD_DSI_TE, DSI_TE, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_45, PAD_LCM_RST, LCM_RST, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_46, PAD_INT_SIM2, MD_INT2_C2K_UIM1_HOT_PLUG, URXD1, UCTS1, CCU_UTXD_AO, TP_UCTS1_AO, IDDIG, I2S5_LRCK),
+ PINMUX_CONSTANTS(GPIO_PAD_47, PAD_INT_SIM1, MD_INT1_C2K_UIM0_HOT_PLUG, UTXD1, URTS1, CCU_URXD_AO, TP_URTS1_AO, USB_DRVVBUS, I2S5_DO),
+ PINMUX_CONSTANTS(GPIO_PAD_48, PAD_SCL5, SCL5, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_49, PAD_SDA5, SDA5, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_50, PAD_SCL3, SCL3, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_51, PAD_SDA3, SDA3, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_52, PAD_BPI_ANT2, BPI_ANT2, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_53, PAD_BPI_ANT0, BPI_ANT0, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_54, PAD_BPI_OLAT1, BPI_OLAT1, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_55, PAD_BPI_BUS8, BPI_BUS8, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_56, PAD_BPI_BUS9, BPI_BUS9, SCL_6306, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_57, PAD_BPI_BUS10, BPI_BUS10, SDA_6306, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_58, PAD_RFIC0_BSI_D2, RFIC0_BSI_D2, SPM_BSI_D2, PWM_B, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_59, PAD_RFIC0_BSI_D1, RFIC0_BSI_D1, SPM_BSI_D1, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_60, PAD_RFIC0_BSI_D0, RFIC0_BSI_D0, SPM_BSI_D0, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_61, PAD_MISC_BSI_DO_1, MIPI1_SDATA, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_62, PAD_MISC_BSI_CK_1, MIPI1_SCLK, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_63, PAD_MISC_BSI_DO_0, MIPI0_SDATA, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_64, PAD_MISC_BSI_CK_0, MIPI0_SCLK, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_65, PAD_MISC_BSI_DO_3, MIPI3_SDATA, BPI_OLAT2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_66, PAD_MISC_BSI_CK_3, MIPI3_SCLK, BPI_OLAT3, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_67, PAD_MISC_BSI_DO_2, MIPI2_SDATA, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_68, PAD_MISC_BSI_CK_2, MIPI2_SCLK, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_69, PAD_BPI_BUS7, BPI_BUS7, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_70, PAD_BPI_BUS6, BPI_BUS6, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_71, PAD_BPI_BUS5, BPI_BUS5, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_72, PAD_BPI_BUS4, BPI_BUS4, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_73, PAD_BPI_BUS3, BPI_BUS3, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_74, PAD_BPI_BUS2, BPI_BUS2, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_75, PAD_BPI_BUS1, BPI_BUS1, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_76, PAD_BPI_BUS0, BPI_BUS0, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_77, PAD_BPI_ANT1, BPI_ANT1, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_78, PAD_BPI_OLAT0, BPI_OLAT0, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_79, PAD_BPI_PA_VM1, BPI_PA_VM1, MIPI4_SDATA, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_80, PAD_BPI_PA_VM0, BPI_PA_VM0, MIPI4_SCLK, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_81, PAD_SDA1, SDA1, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_82, PAD_SDA0, SDA0, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_83, PAD_SCL0, SCL0, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_84, PAD_SCL1, SCL1, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_85, PAD_SPI_MI, SPI0_MI, SCP_SPI0_MI, CLKM3, I2S1_BCK, MFG_DFD_JTAG_TDO, DFD_TDO, JTDO_SEL1),
+ PINMUX_CONSTANTS(GPIO_PAD_86, PAD_SPI_CSB, SPI0_CSB, SCP_SPI0_CS, CLKM0, I2S1_LRCK, MFG_DFD_JTAG_TMS, DFD_TMS, JTMS_SEL1),
+ PINMUX_CONSTANTS(GPIO_PAD_87, PAD_SPI_MO, SPI0_MO, SCP_SPI0_MO, SDA1, I2S1_DO, MFG_DFD_JTAG_TDI, DFD_TDI, JTDI_SEL1),
+ PINMUX_CONSTANTS(GPIO_PAD_88, PAD_SPI_CLK, SPI0_CLK, SCP_SPI0_CK, SCL1, I2S1_MCK, MFG_DFD_JTAG_TCK, DFD_TCK_XI, JTCK_SEL1),
+ PINMUX_CONSTANTS(GPIO_PAD_89, PAD_SRCLKENAI, SRCLKENAI0, PWM_C, I2S5_BCK, ANT_SEL6, SDA8, CMVREF0, DBG_MON_A21),
+ PINMUX_CONSTANTS(GPIO_PAD_90, PAD_PWM_A, PWM_A, CMMCLK2, I2S5_LRCK, SCP_VREQ_VAO, SCL8, PTA_RXD, DBG_MON_A22),
+ PINMUX_CONSTANTS(GPIO_PAD_91, PAD_KPROW1, KPROW1, PWM_B, I2S5_DO, ANT_SEL7, CMMCLK3, PTA_TXD, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_92, PAD_KPROW0, KPROW0, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_93, PAD_KPCOL0, KPCOL0, RES2, RES3, RES4, RES5, RES6, DBG_MON_B27),
+ PINMUX_CONSTANTS(GPIO_PAD_94, PAD_KPCOL1, KPCOL1, I2S2_DI2, I2S5_MCK, CMMCLK2, SCP_SPI2_MI, SRCLKENAI1, SPI2_MI),
+ PINMUX_CONSTANTS(GPIO_PAD_95, PAD_URXD0, URXD0, UTXD0, MD_URXD0, MD_URXD1, SSPM_URXD_AO, CCU_URXD_AO, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_96, PAD_UTXD0, UTXD0, URXD0, MD_UTXD0, MD_UTXD1, SSPM_UTXD_AO, CCU_UTXD_AO, DBG_MON_B2),
+ PINMUX_CONSTANTS(GPIO_PAD_97, PAD_CAM_PDN0, UCTS0, I2S2_MCK, IDDIG, CONN_MCU_TDO, SSPM_JTAG_TDO, IO_JTAG_TDO, DBG_MON_B3),
+ PINMUX_CONSTANTS(GPIO_PAD_98, PAD_CAM_PDN1, URTS0, I2S2_BCK, USB_DRVVBUS, CONN_MCU_TMS, SSPM_JTAG_TMS, IO_JTAG_TMS, DBG_MON_B4),
+ PINMUX_CONSTANTS(GPIO_PAD_99, PAD_CAM_CLK0, CMMCLK0, RES2, RES3, CONN_MCU_AICE_TMSC, RES5, RES6, DBG_MON_B28),
+ PINMUX_CONSTANTS(GPIO_PAD_100, PAD_CAM_CLK1, CMMCLK1, PWM_C, MD_INT1_C2K_UIM0_HOT_PLUG, CONN_MCU_AICE_TCKC, RES5, RES6, DBG_MON_B29),
+ PINMUX_CONSTANTS(GPIO_PAD_101, PAD_CAM_RST0, CLKM2, I2S2_LRCK, CMVREF1, CONN_MCU_TCK, SSPM_JTAG_TCK, IO_JTAG_TCK, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_102, PAD_CAM_RST1, CLKM1, I2S2_DI, DVFSRC_EXT_REQ, CONN_MCU_TDI, SSPM_JTAG_TDI, IO_JTAG_TDI, DBG_MON_B8),
+ PINMUX_CONSTANTS(GPIO_PAD_103, PAD_SCL2, SCL2, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_104, PAD_SDA2, SDA2, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_105, PAD_SCL4, SCL4, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_106, PAD_SDA4, SDA4, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_107, PAD_CAM_PDN2, DMIC_CLK, ANT_SEL0, CLKM0, SDA7, EXT_FRAME_SYNC, PWM_A, DBG_MON_B12),
+ PINMUX_CONSTANTS(GPIO_PAD_108, PAD_CAM_CLK2, CMMCLK2, ANT_SEL1, CLKM1, SCL8, DAP_MD32_SWD, PWM_B, DBG_MON_B13),
+ PINMUX_CONSTANTS(GPIO_PAD_109, PAD_CAM_RST2, DMIC_DAT, ANT_SEL2, CLKM2, SDA8, DAP_MD32_SWCK, PWM_C, DBG_MON_B14),
+ PINMUX_CONSTANTS(GPIO_PAD_110, PAD_CAM_PDN3, SCL7, ANT_SEL0, TP_URXD1_AO, USB_DRVVBUS, SRCLKENAI1, KPCOL2, URXD1),
+ PINMUX_CONSTANTS(GPIO_PAD_111, PAD_CAM_CLK3, CMMCLK3, ANT_SEL1, SRCLKENAI0, SCP_VREQ_VAO, MD_INT2_C2K_UIM1_HOT_PLUG, RES6, DVFSRC_EXT_REQ),
+ PINMUX_CONSTANTS(GPIO_PAD_112, PAD_CAM_RST3, SDA7, ANT_SEL2, TP_UTXD1_AO, IDDIG, AGPS_SYNC, KPROW2, UTXD1),
+ PINMUX_CONSTANTS(GPIO_PAD_113, PAD_CONN_TOP_CLK, CONN_TOP_CLK, RES2, SCL6, AUXIF_CLK0, RES5, TP_UCTS1_AO, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_114, PAD_CONN_TOP_DATA, CONN_TOP_DATA, RES2, SDA6, AUXIF_ST0, RES5, TP_URTS1_AO, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_115, PAD_CONN_BT_CLK, CONN_BT_CLK, UTXD1, PTA_TXD, AUXIF_CLK1, DAP_MD32_SWD, TP_UTXD1_AO, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_116, PAD_CONN_BT_DATA, CONN_BT_DATA, IPU_JTAG_TRST, RES3, AUXIF_ST1, DAP_MD32_SWCK, TP_URXD2_AO, DBG_MON_A0),
+ PINMUX_CONSTANTS(GPIO_PAD_117, PAD_CONN_WF_CTRL0, CONN_WF_HB0, IPU_JTAG_TDO, RES3, RES4, RES5, TP_UTXD2_AO, DBG_MON_A4),
+ PINMUX_CONSTANTS(GPIO_PAD_118, PAD_CONN_WF_CTRL1, CONN_WF_HB1, IPU_JTAG_TDI, RES3, RES4, SSPM_URXD_AO, TP_UCTS2_AO, DBG_MON_A5),
+ PINMUX_CONSTANTS(GPIO_PAD_119, PAD_CONN_WF_CTRL2, CONN_WF_HB2, IPU_JTAG_TCK, RES3, RES4, SSPM_UTXD_AO, TP_URTS2_AO, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_120, PAD_CONN_WB_PTA, CONN_WB_PTA, IPU_JTAG_TMS, RES3, RES4, CCU_URXD_AO, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_121, PAD_CONN_HRST_B, CONN_HRST_B, URXD1, PTA_RXD, RES4, CCU_UTXD_AO, TP_URXD1_AO, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_122, PAD_MSDC0_CMD, MSDC0_CMD, PWRMCU_URXD2_AO, ANT_SEL1, RES4, RES5, RES6, DBG_MON_A12),
+ PINMUX_CONSTANTS(GPIO_PAD_123, PAD_MSDC0_DAT0, MSDC0_DAT0, RES2, ANT_SEL0, RES4, RES5, RES6, DBG_MON_A13),
+ PINMUX_CONSTANTS(GPIO_PAD_124, PAD_MSDC0_CLK, MSDC0_CLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_A14),
+ PINMUX_CONSTANTS(GPIO_PAD_125, PAD_MSDC0_DAT2, MSDC0_DAT2, RES2, MRG_CLK, RES4, RES5, RES6, DBG_MON_A15),
+ PINMUX_CONSTANTS(GPIO_PAD_126, PAD_MSDC0_DAT4, MSDC0_DAT4, RES2, ANT_SEL5, RES4, RES5, UFS_MPHY_SCL, DBG_MON_A16),
+ PINMUX_CONSTANTS(GPIO_PAD_127, PAD_MSDC0_DAT6, MSDC0_DAT6, RES2, ANT_SEL4, RES4, RES5, UFS_MPHY_SDA, DBG_MON_A17),
+ PINMUX_CONSTANTS(GPIO_PAD_128, PAD_MSDC0_DAT1, MSDC0_DAT1, RES2, ANT_SEL2, RES4, RES5, UFS_UNIPRO_SDA, DBG_MON_A18),
+ PINMUX_CONSTANTS(GPIO_PAD_129, PAD_MSDC0_DAT5, MSDC0_DAT5, RES2, ANT_SEL3, RES4, RES5, UFS_UNIPRO_SCL, DBG_MON_A23),
+ PINMUX_CONSTANTS(GPIO_PAD_130, PAD_MSDC0_DAT7, MSDC0_DAT7, RES2, MRG_DO, RES4, RES5, RES6, DBG_MON_A24),
+ PINMUX_CONSTANTS(GPIO_PAD_131, PAD_MSDC0_DSL, MSDC0_DSL, RES2, MRG_SYNC, RES4, RES5, RES6, DBG_MON_A25),
+ PINMUX_CONSTANTS(GPIO_PAD_132, PAD_MSDC0_DAT3, MSDC0_DAT3, RES2, MRG_DI, RES4, RES5, RES6, DBG_MON_A26),
+ PINMUX_CONSTANTS(GPIO_PAD_133, PAD_MSDC0_RSTB, MSDC0_RSTB, RES2, AGPS_SYNC, RES4, RES5, RES6, DBG_MON_A27),
+ PINMUX_CONSTANTS(GPIO_PAD_134, PAD_RTC32K_CK, RTC32K_CK, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_135, PAD_WATCHDOG, WATCHDOG, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_136, PAD_AUD_CLK_MOSI, AUD_CLK_MOSI, AUD_CLK_MISO, I2S1_MCK, RES4, RES5, UFS_UNIPRO_SCL, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_137, PAD_AUD_SYNC_MOSI, AUD_SYNC_MOSI, AUD_SYNC_MISO, I2S1_BCK, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_138, PAD_AUD_DAT_MOSI0, AUD_DAT_MOSI0, AUD_DAT_MISO0, I2S1_LRCK, RES4, RES5, RES6, DBG_MON_B24),
+ PINMUX_CONSTANTS(GPIO_PAD_139, PAD_AUD_DAT_MOSI1, AUD_DAT_MOSI1, AUD_DAT_MISO1, I2S1_DO, RES4, RES5, UFS_MPHY_SDA, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_140, PAD_AUD_CLK_MISO, AUD_CLK_MISO, AUD_CLK_MOSI, I2S0_MCK, RES4, RES5, UFS_UNIPRO_SDA, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_141, PAD_AUD_SYNC_MISO, AUD_SYNC_MISO, AUD_SYNC_MOSI, I2S0_BCK, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_142, PAD_AUD_DAT_MISO0, AUD_DAT_MISO0, AUD_DAT_MOSI0, I2S0_LRCK, VOW_DAT_MISO, RES5, RES6, DBG_MON_B25),
+ PINMUX_CONSTANTS(GPIO_PAD_143, PAD_AUD_DAT_MISO1, AUD_DAT_MISO1, AUD_DAT_MOSI1, I2S0_DI, VOW_CLK_MISO, RES5, UFS_MPHY_SCL, DBG_MON_B26),
+ PINMUX_CONSTANTS(GPIO_PAD_144, PAD_PWRAP_SPI0_MI, PWRAP_SPI0_MI, PWRAP_SPI0_MO, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_145, PAD_PWRAP_SPI0_CSN, PWRAP_SPI0_CSN, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_146, PAD_PWRAP_SPI0_MO, PWRAP_SPI0_MO, PWRAP_SPI0_MI, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_147, PAD_PWRAP_SPI0_CK, PWRAP_SPI0_CK, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_148, PAD_SRCLKENA0, SRCLKENA0, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_149, PAD_SRCLKENA1, SRCLKENA1, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_150, PAD_PERIPHERAL_EN0, PWM_A, CMFLASH, CLKM0, RES4, RES5, RES6, DBG_MON_B30),
+ PINMUX_CONSTANTS(GPIO_PAD_151, PAD_PERIPHERAL_EN1, PWM_B, CMVREF0, CLKM1, RES4, RES5, RES6, DBG_MON_B20),
+ PINMUX_CONSTANTS(GPIO_PAD_152, PAD_PERIPHERAL_EN2, PWM_C, CMFLASH, CLKM2, RES4, RES5, RES6, DBG_MON_B21),
+ PINMUX_CONSTANTS(GPIO_PAD_153, PAD_PERIPHERAL_EN3, PWM_A, CMVREF0, CLKM3, RES4, RES5, RES6, DBG_MON_B22),
+ PINMUX_CONSTANTS(GPIO_PAD_154, PAD_SCP_VREQ_VAO, SCP_VREQ_VAO, DVFSRC_EXT_REQ, RES3, RES4, RES5, RES6, DBG_MON_B18),
+ PINMUX_CONSTANTS(GPIO_PAD_155, PAD_ANT_SEL0, ANT_SEL0, DVFSRC_EXT_REQ, CMVREF1, RES4, RES5, RES6, SCP_JTAG_TDI),
+ PINMUX_CONSTANTS(GPIO_PAD_156, PAD_ANT_SEL1, ANT_SEL1, SRCLKENAI0, SCL6, KPCOL2, IDDIG, RES6, SCP_JTAG_TCK),
+ PINMUX_CONSTANTS(GPIO_PAD_157, PAD_ANT_SEL2, ANT_SEL2, SRCLKENAI1, SDA6, KPROW2, USB_DRVVBUS, RES6, SCP_JTAG_TRSTN),
+ PINMUX_CONSTANTS(GPIO_PAD_158, PAD_PERIPHERAL_EN6, ANT_SEL3, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_159, PAD_PERIPHERAL_EN7, ANT_SEL4, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_160, PAD_PERIPHERAL_EN8, ANT_SEL5, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_161, PAD_SPI1_MI, SPI1_A_MI, SCP_SPI1_MI, IDDIG, ANT_SEL6, KPCOL2, PTA_RXD, DBG_MON_B19),
+ PINMUX_CONSTANTS(GPIO_PAD_162, PAD_SPI1_CSB, SPI1_A_CSB, SCP_SPI1_CS, USB_DRVVBUS, ANT_SEL5, KPROW2, PTA_TXD, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_163, PAD_SPI1_MO, SPI1_A_MO, SCP_SPI1_MO, SDA1, ANT_SEL4, CMMCLK2, DMIC_CLK, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_164, PAD_SPI1_CLK, SPI1_A_CLK, SCP_SPI1_CK, SCL1, ANT_SEL3, CMMCLK3, DMIC_DAT, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_165, PAD_PERIPHERAL_EN4, PWM_B, CMMCLK2, SCP_VREQ_VAO, RES4, RES5, TDM_MCK_2nd, SCP_JTAG_TDO),
+ PINMUX_CONSTANTS(GPIO_PAD_166, PAD_PERIPHERAL_EN9, ANT_SEL6, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_167, PAD_RFIC0_BSI_EN, RFIC0_BSI_EN, SPM_BSI_EN, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_168, PAD_RFIC0_BSI_CK, RFIC0_BSI_CK, SPM_BSI_CK, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_169, PAD_PERIPHERAL_EN5, PWM_C, CMMCLK3, CMVREF1, ANT_SEL7, AGPS_SYNC, TDM_BCK_2nd, SCP_JTAG_TMS),
+ PINMUX_CONSTANTS(GPIO_PAD_170, PAD_I2S1_BCK, I2S1_BCK, I2S3_BCK, SCL7, I2S5_BCK, EXT_FRAME_SYNC, TDM_LRCK_2nd, ANT_SEL3),
+ PINMUX_CONSTANTS(GPIO_PAD_171, PAD_I2S1_LRCK, I2S1_LRCK, I2S3_LRCK, SDA7, I2S5_LRCK, URXD1, TDM_DATA0_2nd, ANT_SEL4),
+ PINMUX_CONSTANTS(GPIO_PAD_172, PAD_I2S1_DO, I2S1_DO, I2S3_DO, SCL8, I2S5_DO, UTXD1, TDM_DATA1_2nd, ANT_SEL5),
+ PINMUX_CONSTANTS(GPIO_PAD_173, PAD_I2S1_MCK, I2S1_MCK, I2S3_MCK, SDA8, I2S5_MCK, UCTS0, TDM_DATA2_2nd, ANT_SEL6),
+ PINMUX_CONSTANTS(GPIO_PAD_174, PAD_I2S2_DI, I2S2_DI, I2S0_DI, DVFSRC_EXT_REQ, I2S2_DI2, URTS0, TDM_DATA3_2nd, ANT_SEL7),
+ PINMUX_CONSTANTS(GPIO_PAD_175, PAD_PERIPHERAL_EN12, ANT_SEL7, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_176, PAD_PERIPHERAL_EN13, RES1, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_177, PAD_PERIPHERAL_EN14, RES1, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_178, PAD_PERIPHERAL_EN10, RES1, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_179, PAD_PERIPHERAL_EN11, RES1, RES2, RES3, RES4, RES5, RES6, RES7),
+};
+
+#endif /* SOC_MEDIATEK_MT8183_PINMUX_H */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia2b0d88e9b70c9ad148797d77dc9e79ce1bcb64a
Gerrit-Change-Number: 27417
Gerrit-PatchSet: 1
Gerrit-Owner: Tristan Hsieh <tristan.shieh at mediatek.com>
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