[coreboot-gerrit] Change in coreboot[master]: riscv: add trampoline in MBR block to support boot mode 1

[Jonathan Neuschäfer (Code Review)]

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/27397 )

Change subject: riscv: add trampoline in MBR block to support boot mode 1
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Patch Set 4:

Ok, I remember. My idea for the MBR code was to act like ZSBL to keep the rest of the code simpler because the memory layout upon bootblock entry stays exactly the same:

1. Initialize L2LIM, if it isn't usable right after reset
2. Copy the bootblock from memory-mapped SPI flash to the beginning of L2LIM
3. Jump into L2LIM

It may also be possible to execute the bootblock in place, but then you need to change bootblock.S or a linker script or something else to place the stack in L2LIM, not just after the bootblock as it currently is.


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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86
Gerrit-Change-Number: 27397
Gerrit-PatchSet: 4
Gerrit-Owner: Philipp Hug <philipp at hug.cx>
Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Gerrit-Reviewer: Philipp Hug <philipp at hug.cx>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Sat, 07 Jul 2018 13:44:37 +0000
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