[coreboot-gerrit] Change in coreboot[master]: riscv: add spin lock support

[Jonathan Neuschäfer (Code Review)]

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/27356 )

Change subject: riscv: add spin lock support
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Patch Set 2:

(2 comments)

https://review.coreboot.org/#/c/27356/2/src/arch/riscv/include/arch/smp/spinlock.h
File src/arch/riscv/include/arch/smp/spinlock.h:

https://review.coreboot.org/#/c/27356/2/src/arch/riscv/include/arch/smp/spinlock.h@30
PS2, Line 30: 	} while (atomic_cas(&lock->lock, 0, -1));
As far as I understand it, CAS is not a native operation on RISC-V. What does this compile to?


https://review.coreboot.org/#/c/27356/2/src/arch/riscv/include/arch/smp/spinlock.h@39
PS2, Line 39: 
Some primitives are missing, compared to the x86 pendant, but I think it's ok to add them later, when they're needed.



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I7e93fb8b35c4452f0fe3f7f4bcc6f7aa4e042451
Gerrit-Change-Number: 27356
Gerrit-PatchSet: 2
Gerrit-Owner: Anonymous Coward (1001664)
Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Gerrit-Reviewer: Shawn Chang <citypw at gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Thu, 05 Jul 2018 10:46:56 +0000
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