[coreboot-gerrit] Change in coreboot[master]: intel/i945: add timestamps in romstage

[Patrick Georgi (Code Review)]

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/27330


Change subject: intel/i945: add timestamps in romstage
......................................................................

intel/i945: add timestamps in romstage

It is able to do so if timestamps are initialized.

Change-Id: Ic95313a19646b66dc1633fb680e54bfc61ec90be
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
M src/northbridge/intel/i945/raminit.c
1 file changed, 3 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/27330/1

diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index d7a349ff..05d6609 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -29,6 +29,7 @@
 #include "chip.h"
 #include <cbmem.h>
 #include <device/dram/ddr2.h>
+#include <timestamp.h>
 
 /* Debugging macros. */
 #if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
@@ -2728,6 +2729,7 @@
 	struct sys_info sysinfo;
 	u8 reg8;
 
+	timestamp_add_now(TS_BEFORE_INITRAM);
 	printk(BIOS_DEBUG, "Setting up RAM controller.\n");
 
 	memset(&sysinfo, 0, sizeof(sysinfo));
@@ -2829,4 +2831,5 @@
 	printk(BIOS_DEBUG, "RAM initialization finished.\n");
 
 	sdram_setup_processor_side();
+	timestamp_add_now(TS_AFTER_INITRAM);
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic95313a19646b66dc1633fb680e54bfc61ec90be
Gerrit-Change-Number: 27330
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Georgi <pgeorgi at google.com>
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