[coreboot-gerrit] Change in coreboot[master]: cpu/intel/socket_FCBGA559: Use common CAR implementation

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23476


Change subject: cpu/intel/socket_FCBGA559: Use common CAR implementation
......................................................................

cpu/intel/socket_FCBGA559: Use common CAR implementation

Tested on Intel D510MO, still boots.

Change-Id: I1ff50c9480e4c2006d8bd4ccedc4884440763874
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/socket_FCBGA559/Kconfig
M src/cpu/intel/socket_FCBGA559/Makefile.inc
2 files changed, 2 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/23476/1

diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig
index d1cc80f..5155daa 100644
--- a/src/cpu/intel/socket_FCBGA559/Kconfig
+++ b/src/cpu/intel/socket_FCBGA559/Kconfig
@@ -8,6 +8,7 @@
 	select CPU_INTEL_MODEL_106CX
 	select MMX
 	select SSE
+	select CPU_INTEL_COMMON_CAR
 
 config DCACHE_RAM_BASE
 	hex
diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc
index dbf300b..87e1939 100644
--- a/src/cpu/intel/socket_FCBGA559/Makefile.inc
+++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc
@@ -8,5 +8,5 @@
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
-cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
+subdirs-y += ../car
 romstage-y += ../car/romstage.c

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1ff50c9480e4c2006d8bd4ccedc4884440763874
Gerrit-Change-Number: 23476
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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