[coreboot-gerrit] Change in coreboot[master]: nb/intel/i945: Use postcar stage to tear down CAR
Arthur Heymans (Code Review)
gerrit at coreboot.org
Sun Jan 28 00:33:26 CET 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23471
Change subject: nb/intel/i945: Use postcar stage to tear down CAR
......................................................................
nb/intel/i945: Use postcar stage to tear down CAR
Tested on Intel d945gclf: still boots.
Change-Id: Ibfa54d48377a9bac62bfa5de667f089ed3ae52ed
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/northbridge/intel/i945/Kconfig
M src/northbridge/intel/i945/Makefile.inc
M src/northbridge/intel/i945/ram_calc.c
3 files changed, 8 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/23471/1
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 482f98a..e04d0c3 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -28,6 +28,8 @@
select RELOCATABLE_RAMSTAGE
select INTEL_EDID
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
+ select POSTCAR_STAGE
+ select POSTCAR_CONSOLE
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
def_bool n
diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc
index 0e4fcfc..ffeabdc 100644
--- a/src/northbridge/intel/i945/Makefile.inc
+++ b/src/northbridge/intel/i945/Makefile.inc
@@ -29,4 +29,6 @@
smm-y += udelay.c
+postcar-y += ram_calc.c
+
endif
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index 990df97..fccd388 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -78,8 +78,6 @@
return ggc2uma[gms] << 10;
}
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
/* setup_stack_and_mtrrs() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use. */
void *setup_stack_and_mtrrs(void)
@@ -87,7 +85,7 @@
struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+ if (postcar_frame_init(&pcf, 1 * KiB))
die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
@@ -106,8 +104,7 @@
postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
- /* Save the number of MTRRs to setup. Return the stack location
- * pointing to the number of MTRRs.
- */
- return postcar_commit_mtrrs(&pcf);
+ run_postcar_phase(&pcf);
+ /* Needs to return something but we never go back to the caller */
+ return NULL;
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ibfa54d48377a9bac62bfa5de667f089ed3ae52ed
Gerrit-Change-Number: 23471
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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