[coreboot-gerrit] Change in coreboot[master]: cpu/intel/socket_mPGA478mn, socket_BGA956: Use common CAR code

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23454


Change subject: cpu/intel/socket_mPGA478mn,socket_BGA956: Use common CAR code
......................................................................

cpu/intel/socket_mPGA478mn,socket_BGA956: Use common CAR code

Change-Id: Icc768a88820ea70db15597e4f42b9d29abba796e
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/socket_BGA956/Kconfig
M src/cpu/intel/socket_BGA956/Makefile.inc
M src/cpu/intel/socket_mPGA478MN/Kconfig
M src/cpu/intel/socket_mPGA478MN/Makefile.inc
4 files changed, 6 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/23454/1

diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig
index 6c5e414..b62db66 100644
--- a/src/cpu/intel/socket_BGA956/Kconfig
+++ b/src/cpu/intel/socket_BGA956/Kconfig
@@ -3,6 +3,8 @@
 	select CPU_INTEL_MODEL_1067X
 	select MMX
 	select SSE
+	select CPU_INTEL_COMMON_CAR
+	select CPU_HAS_L2_CACHE_MSR
 
 if CPU_INTEL_SOCKET_BGA956
 
diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc
index 22c1a7c..4c98c4a 100644
--- a/src/cpu/intel/socket_BGA956/Makefile.inc
+++ b/src/cpu/intel/socket_BGA956/Makefile.inc
@@ -8,6 +8,5 @@
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
-# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
-cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+subdirs-y += ../car
 romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_mPGA478MN/Kconfig b/src/cpu/intel/socket_mPGA478MN/Kconfig
index 7d97022..022908c3 100644
--- a/src/cpu/intel/socket_mPGA478MN/Kconfig
+++ b/src/cpu/intel/socket_mPGA478MN/Kconfig
@@ -4,6 +4,8 @@
 	select CPU_INTEL_MODEL_6FX
 	select MMX
 	select SSE
+	select CPU_INTEL_COMMON_CAR
+	select CPU_HAS_L2_CACHE_MSR
 
 if CPU_INTEL_SOCKET_MPGA478MN
 
diff --git a/src/cpu/intel/socket_mPGA478MN/Makefile.inc b/src/cpu/intel/socket_mPGA478MN/Makefile.inc
index 407861e..3c58ba8 100644
--- a/src/cpu/intel/socket_mPGA478MN/Makefile.inc
+++ b/src/cpu/intel/socket_mPGA478MN/Makefile.inc
@@ -9,6 +9,5 @@
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
-# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
-cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+subdirs-y += ../car
 romstage-y += ../car/romstage.c

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Icc768a88820ea70db15597e4f42b9d29abba796e
Gerrit-Change-Number: 23454
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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