[coreboot-gerrit] Change in coreboot[master]: nb/intel/gm45: Use postcar stage to tear down CAR

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23455


Change subject: nb/intel/gm45: Use postcar stage to tear down CAR
......................................................................

nb/intel/gm45: Use postcar stage to tear down CAR

Change-Id: I1e848dcadeffb092b98bc5868e370dffce44a0c0
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/northbridge/intel/gm45/Kconfig
M src/northbridge/intel/gm45/Makefile.inc
M src/northbridge/intel/gm45/ram_calc.c
3 files changed, 11 insertions(+), 10 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/23455/1

diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 85902d3..193ec70 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -29,6 +29,8 @@
 	select RELOCATABLE_RAMSTAGE
 	select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
 	select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
+	select POSTCAR_STAGE
+	select POSTCAR_CONSOLE
 
 config CBFS_SIZE
 	hex
diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc
index fdf0012..c12bbf1 100644
--- a/src/northbridge/intel/gm45/Makefile.inc
+++ b/src/northbridge/intel/gm45/Makefile.inc
@@ -36,4 +36,6 @@
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/lapic/apic_timer.c
 
+postcar-y += ram_calc.c
+
 endif
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index 780bed4..5ec11a4 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -95,8 +95,6 @@
 	return (void *) top_of_ram;
 }
 
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
 /* setup_stack_and_mtrrs() determines the stack to use after
  * cache-as-ram is torn down as well as the MTRR settings to use. */
 void *setup_stack_and_mtrrs(void)
@@ -104,7 +102,7 @@
 	struct postcar_frame pcf;
 	uintptr_t top_of_ram;
 
-	if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+	if (postcar_frame_init(&pcf, 1*KiB))
 		die("Unable to initialize postcar frame.\n");
 
 	/* Cache the ROM as WP just below 4GiB. */
@@ -114,17 +112,16 @@
 	/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
 	postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
 
-	/* Cache two separate 4 MiB regions below the top of ram, this
+	/* Cache a 16MiB region below the top of ram, this
 	 * satisfies MTRR alignment requirements. If you modify this to
 	 * cover TSEG, make sure UMA region is not set with WRBACK as it
 	 * causes hard-to-recover boot failures.
 	 */
 	top_of_ram = (uintptr_t)cbmem_top();
-	postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
-	postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
+	printk(BIOS_DEBUG, "top_of_ram = 0x%x\n", (u32)top_of_ram);
+	postcar_frame_add_mtrr(&pcf, top_of_ram - 16 * MiB, 16 * MiB,
+			MTRR_TYPE_WRBACK);
 
-	/* Save the number of MTRRs to setup. Return the stack location
-	 * pointing to the number of MTRRs.
-	 */
-	return postcar_commit_mtrrs(&pcf);
+	/* Needs to return something but we never go back to the caller */
+	return NULL;
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1e848dcadeffb092b98bc5868e370dffce44a0c0
Gerrit-Change-Number: 23455
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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