[coreboot-gerrit] Change in coreboot[master]: intel/sandybridge: Tear down CAR in a separate postcar stage
Arthur Heymans (Code Review)
gerrit at coreboot.org
Fri Jan 26 17:00:50 CET 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23450
Change subject: intel/sandybridge: Tear down CAR in a separate postcar stage
......................................................................
intel/sandybridge: Tear down CAR in a separate postcar stage
This adds some code to the common Intel CAR code to tear down CAR.
Tested on Thinkpad X220: still boots.
Change-Id: Ieefe0564af3470cba484eea131802f1529dbe22c
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/car/Makefile.inc
M src/cpu/intel/car/cache_as_ram.S
M src/cpu/intel/car/romstage.c
A src/cpu/intel/car/teardown_car.S
M src/northbridge/intel/sandybridge/Kconfig
M src/northbridge/intel/sandybridge/Makefile.inc
M src/northbridge/intel/sandybridge/ram_calc.c
M src/northbridge/intel/sandybridge/romstage.c
8 files changed, 102 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/23450/1
diff --git a/src/cpu/intel/car/Makefile.inc b/src/cpu/intel/car/Makefile.inc
index 2623fe3..719972d 100644
--- a/src/cpu/intel/car/Makefile.inc
+++ b/src/cpu/intel/car/Makefile.inc
@@ -1 +1,2 @@
cpu_incs-y += $(src)/cpu/intel/car/common_cache_as_ram.inc
+postcar-y += teardown_car.S
diff --git a/src/cpu/intel/car/cache_as_ram.S b/src/cpu/intel/car/cache_as_ram.S
index 7397cf0..c175587 100644
--- a/src/cpu/intel/car/cache_as_ram.S
+++ b/src/cpu/intel/car/cache_as_ram.S
@@ -188,6 +188,10 @@
/* Call romstage.c main function. */
call romstage_main
+#if IS_ENABLED(CONFIG_POSTCAR_STAGE)
+ /* We don't return here */
+ jmp postcar_entry_failure
+#endif
/* Save return value from romstage_main. It contains the stack to use
* after cache-as-ram is torn down. It also contains the information
* for setting up MTRRs. */
@@ -313,6 +317,7 @@
cld /* Clear direction flag. */
call romstage_after_car
+postcar_entry_failure:
.Lhlt:
post_code(POST_DEAD_CODE)
hlt
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 555c384..45b6de2 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -23,7 +23,9 @@
asmlinkage void *romstage_main(unsigned long bist)
{
int i;
+#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)
void *romstage_stack_after_car;
+#endif
const int num_guards = 4;
const u32 stack_guard = 0xdeadbeef;
u32 *stack_base;
@@ -53,9 +55,12 @@
}
/* Get the stack to use after cache-as-ram is torn down. */
+#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)
romstage_stack_after_car = setup_stack_and_mtrrs();
return romstage_stack_after_car;
+#endif
+ return NULL;
}
asmlinkage void romstage_after_car(void)
diff --git a/src/cpu/intel/car/teardown_car.S b/src/cpu/intel/car/teardown_car.S
new file mode 100644
index 0000000..a1097b0
--- /dev/null
+++ b/src/cpu/intel/car/teardown_car.S
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
+
+#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
+
+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+
+.global chipset_teardown_car
+chipset_teardown_car:
+ pop %esp
+
+ post_code(0x30)
+
+ /* Disable cache. */
+ movl %cr0, %eax
+ orl $CR0_CacheDisable, %eax
+ movl %eax, %cr0
+
+ post_code(0x31)
+
+ /* Disable MTRR. */
+ movl $MTRR_DEF_TYPE_MSR, %ecx
+ rdmsr
+ andl $(~MTRR_DEF_TYPE_EN), %eax
+ wrmsr
+
+#if IS_ENABLED(CONFIG_HAS_NO_EVICT_MODE)
+ /* Disable the no eviction run state */
+ movl $NoEvictMod_MSR, %ecx
+ rdmsr
+ andl $~2, %eax
+ wrmsr
+ andl $~1, %eax
+ wrmsr
+#endif
+
+ post_code(0x32)
+
+ /* Return to caller. */
+ jmp *%esp
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 043e8de..076979c 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -21,6 +21,7 @@
select HAVE_DEBUG_RAM_SETUP
select INTEL_GMA_ACPI
select RELOCATABLE_RAMSTAGE
+ select POSTCAR_STAGE
config NORTHBRIDGE_INTEL_IVYBRIDGE
bool
@@ -29,6 +30,7 @@
select HAVE_DEBUG_RAM_SETUP
select INTEL_GMA_ACPI
select RELOCATABLE_RAMSTAGE
+ select POSTCAR_STAGE
if NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index 846d31b..c2750de 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -57,4 +57,6 @@
mrc.cache-type := mrc_cache
endif
+postcar-y += ram_calc.c
+
endif
diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c
index 43442f1..1858abc 100644
--- a/src/northbridge/intel/sandybridge/ram_calc.c
+++ b/src/northbridge/intel/sandybridge/ram_calc.c
@@ -43,42 +43,3 @@
{
return (void *) smm_region_start();
}
-
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
-/* setup_stack_and_mtrrs() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use. */
-void *setup_stack_and_mtrrs(void)
-{
- struct postcar_frame pcf;
- uintptr_t top_of_ram;
-
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
- die("Unable to initialize postcar frame.\n");
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,
- MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
- top_of_ram = (uintptr_t)cbmem_top();
- /* Cache 8MiB below the top of ram. On sandybridge systems the top of
- * ram under 4GiB is the start of the TSEG region. It is required to
- * be 8MiB aligned. Set this area as cacheable so it can be used later
- * for ramstage before setting up the entire RAM as cacheable. */
- postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
-
- /* Cache 8MiB at the top of ram. Top of ram on sandybridge systems
- * is where the TSEG region resides. However, it is not restricted
- * to SMM mode until SMM has been relocated. By setting the region
- * to cacheable it provides faster access when relocating the SMM
- * handler as well as using the TSEG region for other purposes. */
- postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
-
- /* Save the number of MTRRs to setup. Return the stack location
- * pointing to the number of MTRRs.
- */
- return postcar_commit_mtrrs(&pcf);
-}
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 0426b83..d7e523f 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -15,12 +15,15 @@
* GNU General Public License for more details.
*/
+#include <assert.h>
#include <stdint.h>
#include <string.h>
#include <console/console.h>
+#include <cbmem.h>
#include <arch/io.h>
#include <lib.h>
#include <cpu/x86/lapic.h>
+#include <cpu/x86/mtrr.h>
#include <timestamp.h>
#include "sandybridge.h"
#include <cpu/x86/bist.h>
@@ -46,8 +49,13 @@
/* Platform has no romstage entry point under mainboard directory,
* so this one is named with prefix mainboard.
*/
+
+#define ROMSTAGE_RAM_STACK_SIZE 0x5000
+
void mainboard_romstage_entry(unsigned long bist)
{
+ u32 top_of_ram;
+ struct postcar_frame pcf;
int s3resume = 0;
if (MCHBAR16(SSKPD) == 0xCAFE) {
@@ -122,4 +130,25 @@
}
post_code(0x3f);
+
+ if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+ die("Unable to initialize postcar frame.\n");
+
+ /* Cache the ROM as WP just below 4GiB. */
+ postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,
+ MTRR_TYPE_WRPROT);
+
+ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
+ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+
+ /* Cache a 16MiB region below the top of ram, this
+ * satisfies MTRR alignment requirements. If you modify this to
+ * cover TSEG, make sure UMA region is not set with WRBACK as it
+ * causes hard-to-recover boot failures.
+ */
+ top_of_ram = (uintptr_t)cbmem_top();
+ printk(BIOS_DEBUG, "top_of_ram = 0x%x\n", top_of_ram);
+ postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK);
+
+ run_postcar_phase(&pcf);
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ieefe0564af3470cba484eea131802f1529dbe22c
Gerrit-Change-Number: 23450
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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