[coreboot-gerrit] Change in coreboot[master]: cpu/intel: Move the Sandy Bridge CAR to a common place
Arthur Heymans (Code Review)
gerrit at coreboot.org
Fri Jan 26 17:00:49 CET 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23449
Change subject: cpu/intel: Move the Sandy Bridge CAR to a common place
......................................................................
cpu/intel: Move the Sandy Bridge CAR to a common place
CAR can be reused over a wide range of CPU generations.
This adds a Kconfig file to select some code paths to take that
differ accross CPU's.
Change-Id: I68ae66f2620ed061a54d07025295a0eb8f64fa62
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/Kconfig
A src/cpu/intel/car/Kconfig
A src/cpu/intel/car/Makefile.inc
R src/cpu/intel/car/cache_as_ram.S
A src/cpu/intel/car/common_cache_as_ram.inc
M src/cpu/intel/model_206ax/Kconfig
M src/cpu/intel/model_206ax/Makefile.inc
7 files changed, 59 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/23449/1
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index 612b62e..8a07d9a 100644
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -46,3 +46,5 @@
source src/cpu/intel/fit/Kconfig
source src/cpu/intel/turbo/Kconfig
source src/cpu/intel/common/Kconfig
+
+source src/cpu/intel/car/Kconfig
diff --git a/src/cpu/intel/car/Kconfig b/src/cpu/intel/car/Kconfig
new file mode 100644
index 0000000..04ab95d
--- /dev/null
+++ b/src/cpu/intel/car/Kconfig
@@ -0,0 +1,29 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+
+config CPU_INTEL_COMMON_CAR
+ bool
+
+if CPU_INTEL_COMMON_CAR
+
+config HAS_L2_CACHE_MSR
+ bool
+
+config HAS_NO_EVICT_MODE
+ bool
+
+config HAS_20_VARIABLE_MTRR
+ bool
+
+endif
diff --git a/src/cpu/intel/car/Makefile.inc b/src/cpu/intel/car/Makefile.inc
new file mode 100644
index 0000000..2623fe3
--- /dev/null
+++ b/src/cpu/intel/car/Makefile.inc
@@ -0,0 +1 @@
+cpu_incs-y += $(src)/cpu/intel/car/common_cache_as_ram.inc
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.S
similarity index 93%
rename from src/cpu/intel/model_206ax/cache_as_ram.inc
rename to src/cpu/intel/car/cache_as_ram.S
index d1678bf..7397cf0 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.S
@@ -33,6 +33,7 @@
#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
#define NoEvictMod_MSR 0x2e0
+#define MSR_BBL_CR_CTL3 0x11e
/* Save the BIST result. */
movl %eax, %ebp
@@ -94,18 +95,28 @@
orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
+#if IS_ENABLED(CONFIG_HAS_L2_CACHE_MSR)
+ /* Enable L2 cache. */
+ movl $MSR_BBL_CR_CTL3, %ecx
+ rdmsr
+ orl $(1 << 8), %eax
+ wrmsr
+#endif
+
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
movl %cr0, %eax
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
invd
movl %eax, %cr0
+#if IS_ENABLED(CONFIG_HAS_NO_EVICT_MODE)
/* enable the 'no eviction' mode */
movl $NoEvictMod_MSR, %ecx
rdmsr
orl $1, %eax
andl $~2, %eax
wrmsr
+#endif
/* Clear the cache memory region. This will also fill up the cache. */
movl $CACHE_AS_RAM_BASE, %esi
@@ -115,11 +126,13 @@
xorl %eax, %eax
rep stosl
+#if IS_ENABLED(CONFIG_HAS_NO_EVICT_MODE)
/* enable the 'no eviction run' state */
movl $NoEvictMod_MSR, %ecx
rdmsr
orl $3, %eax
wrmsr
+#endif
post_code(0x26)
/* Enable Cache-as-RAM mode by disabling cache. */
@@ -174,6 +187,7 @@
post_code(0x29)
/* Call romstage.c main function. */
call romstage_main
+
/* Save return value from romstage_main. It contains the stack to use
* after cache-as-ram is torn down. It also contains the information
* for setting up MTRRs. */
@@ -196,18 +210,22 @@
post_code(0x32)
+#if IS_ENABLED(CONFIG_HAS_NO_EVICT_MODE)
/* Disable the no eviction run state */
movl $NoEvictMod_MSR, %ecx
rdmsr
andl $~2, %eax
wrmsr
+#endif
invd
+#if IS_ENABLED(CONFIG_HAS_NO_EVICT_MODE)
/* Disable the no eviction mode */
rdmsr
andl $~1, %eax
wrmsr
+#endif
post_code(0x33)
@@ -311,5 +329,9 @@
.word 0x204, 0x205, 0x206, 0x207
.word 0x208, 0x209, 0x20A, 0x20B
.word 0x20C, 0x20D, 0x20E, 0x20F
+#if !IS_ENABLED(HAS_20_VARIABLE_MTRR)
+mtrr_table_end:
+#else
.word 0x210, 0x211, 0x212, 0x213
mtrr_table_end:
+#endif
diff --git a/src/cpu/intel/car/common_cache_as_ram.inc b/src/cpu/intel/car/common_cache_as_ram.inc
new file mode 100644
index 0000000..03beacc
--- /dev/null
+++ b/src/cpu/intel/car/common_cache_as_ram.inc
@@ -0,0 +1 @@
+#include "cache_as_ram.S"
\ No newline at end of file
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index f16b119..546ee6f 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -22,6 +22,9 @@
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select CPU_INTEL_COMMON
+ select CPU_INTEL_COMMON_CAR
+ select CPU_HAS_NO_EVICT_MODE
+ select CPU_HAS_20_VARIABLE_MTRR
config BOOTBLOCK_CPU_INIT
string
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 7516e9d..9bcbded 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -14,5 +14,5 @@
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
-cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
+subdirs-y += ../car
romstage-y += ../car/romstage.c
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I68ae66f2620ed061a54d07025295a0eb8f64fa62
Gerrit-Change-Number: 23449
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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