[coreboot-gerrit] Change in coreboot[master]: mainboard/google/meowth: Turn on DBC over USB3.0

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/23446


Change subject: mainboard/google/meowth: Turn on DBC over USB3.0
......................................................................

mainboard/google/meowth: Turn on DBC over USB3.0

Intel DCI(direct connect interface) allows debug Intel target using
USB3.0 ports. It will support debug via USB stack(DCI Dbc) using USB3.0
only.

BUG=None
TEST=Turn on DCI trace hub in descriptor.bin and flash the coreboot
image. Using DAL to halt/run CPU.

Change-Id: I39e68dabfcb9e659733019334299e562eee3681d
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/mainboard/google/zoombini/variants/meowth/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/23446/1

diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
index aed4a19..72cfb96 100644
--- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
+++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
@@ -6,6 +6,9 @@
 	register "deep_s5_enable_ac" = "1"
 	register "deep_s5_enable_dc" = "1"
 
+	# Debug Option, set to DBC over USB 3.0 port only
+	register "DebugConsent" = "3"
+
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this
 	# route. i.e. If this route changes then the affected GPE

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I39e68dabfcb9e659733019334299e562eee3681d
Gerrit-Change-Number: 23446
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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