[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Add chipset region to SMM map

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/23438


Change subject: amd/stoneyridge: Add chipset region to SMM map
......................................................................

amd/stoneyridge: Add chipset region to SMM map

Make room for a region where S3 volatile data may be stored inside the
TSEG range.

BUG=b:69614064

Change-Id: I096beb6b6c9543d0116a9e91fdf5949a63b2c488
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/ramtop.c
1 file changed, 24 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/23438/1

diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c
index e676465..5ae6e5a 100644
--- a/src/soc/amd/stoneyridge/ramtop.c
+++ b/src/soc/amd/stoneyridge/ramtop.c
@@ -21,6 +21,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cbmem.h>
+#include <amdblocks/s3_resume.h>
 #include <soc/northbridge.h>
 #include <soc/southbridge.h>
 
@@ -62,11 +63,26 @@
 	*size = smm_region_size();
 }
 
+/*
+ * SMM region top     +----------------------+
+ *                    |   Chipset-specific   |
+ *                    +----------------------+
+ *                    |   Cache              |
+ *                    +----------------------+
+ *                    |                      |
+ *                    |   SMM Handler        |
+ *                    |                      |
+ * SMM Region start   +----------------------+
+ *   (cbmem top)
+ */
+
 int smm_subregion(int sub, void **start, size_t *size)
 {
 	uintptr_t sub_base;
 	size_t sub_size;
 	const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
+	const size_t chip_size = IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) ?
+					S3_VOLATILE_SIZE : 0;
 
 	sub_base = smm_region_start();
 	sub_size = smm_region_size();
@@ -76,13 +92,19 @@
 	switch (sub) {
 	case SMM_SUBREGION_HANDLER:
 		/* Handler starts at the base of TSEG. */
-		sub_size -= cache_size;
+		sub_size -= cache_size + chip_size;
 		break;
 	case SMM_SUBREGION_CACHE:
 		/* External cache is in the middle of TSEG. */
-		sub_base += sub_size - cache_size;
+		sub_base += sub_size - cache_size - chip_size;
 		sub_size = cache_size;
 		break;
+	case SMM_SUBREGION_CHIPSET:
+		if (!IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
+			return -1;
+		sub_base += sub_size - chip_size;
+		sub_size = chip_size;
+		break;
 	default:
 		return -1;
 	}

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I096beb6b6c9543d0116a9e91fdf5949a63b2c488
Gerrit-Change-Number: 23438
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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