[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Convert BiosRam access to MMIO

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/23436


Change subject: amd/stoneyridge: Convert BiosRam access to MMIO
......................................................................

amd/stoneyridge: Convert BiosRam access to MMIO

Change the BiosRam read/write functions to use the fixed MMIO range at
0xfed80500.  This is faster than two accesses per byte when using I/O
0xcd4/0xcd5.

Note that BiosRam may only be accessed byte-by-byte.  It does not decode
normally.

Change-Id: I9d8baf2bd5d9d48a87bddfb6a0b86e292a8fdf7d
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/include/soc/iomap.h
M src/soc/amd/stoneyridge/sb_util.c
2 files changed, 5 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/23436/1

diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index 2d42ad9..e121fa0 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -36,6 +36,7 @@
 #define AMD_SB_ACPI_MMIO_ADDR		0xfed80000
 #define APU_SMI_BASE			0xfed80200
 #define PM_MMIO_BASE			0xfed80300
+#define BIOSRAM_MMIO_BASE		0xfed80500
 #define XHCI_ACPI_PM_MMIO_BASE		0xfed81c00
 #define APU_UART0_BASE			0xfedc6000
 #define APU_UART1_BASE			0xfedc8000
diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c
index 5238506..5e52a28 100644
--- a/src/soc/amd/stoneyridge/sb_util.c
+++ b/src/soc/amd/stoneyridge/sb_util.c
@@ -76,18 +76,18 @@
 	write8((void *)(APU_SMI_BASE + offset), value);
 }
 
+
 uint8_t biosram_read8(uint8_t offset)
 {
-	outb(offset, BIOSRAM_INDEX);
-	return inb(BIOSRAM_DATA);
+	return read8((void *)(BIOSRAM_MMIO_BASE + offset));
 }
 
 void biosram_write8(uint8_t offset, uint8_t value)
 {
-	outb(offset, BIOSRAM_INDEX);
-	outb(value, BIOSRAM_DATA);
+	write8((void *)(BIOSRAM_MMIO_BASE + offset), value);
 }
 
+/* BiosRam may only be accessed a byte at a time */
 uint16_t biosram_read16(uint8_t offset)
 {
 	int i;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9d8baf2bd5d9d48a87bddfb6a0b86e292a8fdf7d
Gerrit-Change-Number: 23436
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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