[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add more HDA Audio Link settings

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/23400


Change subject: soc/intel/cannonlake: Add more HDA Audio Link settings
......................................................................

soc/intel/cannonlake: Add more HDA Audio Link settings

FSP have exposed more HDA Audio link option, included that into
coreboot. Users can modify that base on platform implementations.

BUG=None
TEST=Boot up with debug build version FSP and check the debug print
result.

Change-Id: Ib2a75f554ddf9919a62c78a162ec1b9e602f1f5d
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/chip.h
2 files changed, 18 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/23400/1

diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 2810ed1..6d78f95 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -212,6 +212,15 @@
 	/* Audio */
 	params->PchHdaDspEnable = config->PchHdaDspEnable;
 	params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda;
+	params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0;
+	params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1;
+	params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0;
+	params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1;
+	params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2;
+	params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1;
+	params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2;
+	params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;
+	params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;
 
 	/* USB */
 	for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index a42494c..7930002 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -138,6 +138,15 @@
 
 	/* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */
 	uint8_t PchHdaAudioLinkHda;
+	uint8_t PchHdaAudioLinkDmic0;
+	uint8_t PchHdaAudioLinkDmic1;
+	uint8_t PchHdaAudioLinkSsp0;
+	uint8_t PchHdaAudioLinkSsp1;
+	uint8_t PchHdaAudioLinkSsp2;
+	uint8_t PchHdaAudioLinkSndw1;
+	uint8_t PchHdaAudioLinkSndw2;
+	uint8_t PchHdaAudioLinkSndw3;
+	uint8_t PchHdaAudioLinkSndw4;
 
 	/* PCIe Root Ports */
 	uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib2a75f554ddf9919a62c78a162ec1b9e602f1f5d
Gerrit-Change-Number: 23400
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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