[coreboot-gerrit] Change in coreboot[master]: mainboard/google/zoombini/variants/meowth: Fix USB OC settings

[Nick Vaccaro (Code Review)]

Hello Nick Vaccaro,

I'd like you to do a code review. Please visit

    https://review.coreboot.org/23390

to review the following change.


Change subject: mainboard/google/zoombini/variants/meowth: Fix USB OC settings
......................................................................

mainboard/google/zoombini/variants/meowth: Fix USB OC settings

Set USB2 port 0 & 1 to use OC2 and OC3 respectively.  Previous settings
were causing false overcurrent conditions as OC0 and OC1 were used for
other purposes.

Remove initialization of unused usb3 ports, and configure the ports we
use (usb3 ports 0 & 1) to use OC2 and OC3, respectively.

BUG=b:72250084
BRANCH=none
TEST=Verify meowth can recognize and boot off a kernel on USB drive.

Change-Id: I528b67d80a1da84e5307facb40de545089979f57
Signed-off-by: Nick Vaccaro <nvaccaro at chromium.org>
---
M src/mainboard/google/zoombini/variants/meowth/devicetree.cb
1 file changed, 5 insertions(+), 9 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/23390/1

diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
index b2c1f06..bccd8a6 100644
--- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
+++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
@@ -39,9 +39,9 @@
 		.early_init = 1,
 	}"
 
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
-	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"
-	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)"
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC3)"
+	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"
 	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"
 	register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)"
 	register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)"
@@ -50,12 +50,8 @@
 	register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"
 	register "usb2_ports[9]" = "USB2_PORT_TYPE_C(OC_SKIP)"
 
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)"
 
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I528b67d80a1da84e5307facb40de545089979f57
Gerrit-Change-Number: 23390
Gerrit-PatchSet: 1
Gerrit-Owner: Nick Vaccaro <nvaccaro at google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro at chromium.org>
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