[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: CannonaLake make use of FVI information

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/23387


Change subject: soc/intel/cannonlake: CannonaLake make use of FVI information
......................................................................

soc/intel/cannonlake: CannonaLake make use of FVI information

Select DISPLAY_FSP_VERSION_INFO Kconfig to get all required
firmware information right after FSP-S.

TEST=Display FW information as below

>> Display FSP Version Info HOB
Reference Code - CPU = 7.1.20.52
uCode Version = 0.0.0.16
Reference Code - ME 11.0 = 7.1.20.52
MEBx version = 0.0.0.0
ME Firmware Version = Consumer SKU
Reference Code - CNL PCH = 7.1.20.52
PCH-CRID Status = Disabled
CNL PCH H A0 Hsio Version = 2.0.0.0
CNL PCH H Ax Hsio Version = 9.0.0.0
CNL PCH H Bx Hsio Version = 5.0.0.0
CNL PCH LP Ax Hsio Version = 13.0.0.0
CNL PCH LP B0 Hsio Version = 7.0.0.0
CNL PCH LP Bx Hsio Version = 6.0.0.0
CNL PCH LP Dx Hsio Version = 2.0.0.0
Reference Code - SA - System Agent = 7.1.20.52
Reference Code - MRC = 0.5.1.19
SA - PCIe Version = 7.1.20.52
SA-CRID Status = Disabled
SA-CRID Original Value = 0.0.0.0
SA-CRID New Value = 0.0.0.0

Change-Id: Ibfcac0002998e8a6594bb6dfc68b2577f62ddbff
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/chip.c
2 files changed, 7 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/23387/1

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index d11f59f..c56ef2e 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -75,6 +75,7 @@
 	select TSC_CONSTANT_RATE
 	select TSC_MONOTONIC_TIMER
 	select UDELAY_TSC
+	select DISPLAY_FSP_VERSION_INFO
 
 config UDK_VERSION
 	int
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 2810ed1..d548be6 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -132,6 +132,12 @@
 {
 	/* Perform silicon specific init. */
 	fsp_silicon_init(romstage_handoff_is_resume());
+
+	 /* Display FIRMWARE_VERSION_INFO_HOB */
+	if (IS_ENABLED(CONFIG_DISPLAY_FSP_VERSION_INFO)) {
+		printk(BIOS_DEBUG, "Display FSP Version Info HOB \n");
+		fsp_find_fvi_version_hob();
+	}
 }
 
 static void pci_domain_set_resources(device_t dev)

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ibfcac0002998e8a6594bb6dfc68b2577f62ddbff
Gerrit-Change-Number: 23387
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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