[coreboot-gerrit] Change in coreboot[master]: src/mainboard/hp: Add hp pavilion g7-2247us support
Marty E. Plummer (Code Review)
gerrit at coreboot.org
Mon Jan 22 07:55:04 CET 2018
Marty E. Plummer has uploaded this change for review. ( https://review.coreboot.org/23352
Change subject: src/mainboard/hp: Add hp pavilion g7-2247us support
......................................................................
src/mainboard/hp: Add hp pavilion g7-2247us support
Mostly straight from autoport, with some adjustments to ec-related code.
ec.{c,h} stolen from google/butterfly, as it is apparently the only
other device that uses the ene kb3940q ec. Needs work, as apparently the
LID0 is stuck in a 'closed' state.
Mostly pushing to get more feedback and suggestions as to how stuff
should be handled.
Change-Id: I6f91595b0c06d683afb74eb54b3b78bd0458d6a1
Signed-off-by: Marty E. Plummer <hanetzer at startmail.com>
---
A src/mainboard/hp/pavilion_g7_2247us/Kconfig
A src/mainboard/hp/pavilion_g7_2247us/Kconfig.name
A src/mainboard/hp/pavilion_g7_2247us/Makefile.inc
A src/mainboard/hp/pavilion_g7_2247us/acpi/ec.asl
A src/mainboard/hp/pavilion_g7_2247us/acpi/mainboard.asl
A src/mainboard/hp/pavilion_g7_2247us/acpi/platform.asl
A src/mainboard/hp/pavilion_g7_2247us/acpi/superio.asl
A src/mainboard/hp/pavilion_g7_2247us/acpi_tables.c
A src/mainboard/hp/pavilion_g7_2247us/board_info.txt
A src/mainboard/hp/pavilion_g7_2247us/devicetree.cb
A src/mainboard/hp/pavilion_g7_2247us/dsdt.asl
A src/mainboard/hp/pavilion_g7_2247us/early_southbridge.c
A src/mainboard/hp/pavilion_g7_2247us/ec.c
A src/mainboard/hp/pavilion_g7_2247us/ec.h
A src/mainboard/hp/pavilion_g7_2247us/gnvs.c
A src/mainboard/hp/pavilion_g7_2247us/gpio.c
A src/mainboard/hp/pavilion_g7_2247us/hda_verb.c
A src/mainboard/hp/pavilion_g7_2247us/mainboard.c
A src/mainboard/hp/pavilion_g7_2247us/romstage.c
19 files changed, 819 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/23352/1
diff --git a/src/mainboard/hp/pavilion_g7_2247us/Kconfig b/src/mainboard/hp/pavilion_g7_2247us/Kconfig
new file mode 100644
index 0000000..6e99f1c
--- /dev/null
+++ b/src/mainboard/hp/pavilion_g7_2247us/Kconfig
@@ -0,0 +1,61 @@
+if BOARD_HP_PAVILION_G7_2247US
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select BOARD_ROMSIZE_KB_4096
+ select CPU_INTEL_SOCKET_RPGA989
+ select EC_QUANTA_ENE_KB3940Q
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_INT15
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select SANDYBRIDGE_IVYBRIDGE_LVDS
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+
+config HAVE_IFD_BIN
+ bool
+ default n
+
+config HAVE_ME_BIN
+ bool
+ default n
+
+config MAINBOARD_DIR
+ string
+ default hp/pavilion_g7_2247us
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "HP Pavilion g7 Notebook PC"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0166.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0166"
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x1843
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x103c
+
+config DRAM_RESET_GATE_GPIO # FIXME: check this
+ int
+ default 60
+
+config MAX_CPUS
+ int
+ default 8
+
+config USBDEBUG_HCD_INDEX # FIXME: check this
+ int
+ default 2
+endif
diff --git a/src/mainboard/hp/pavilion_g7_2247us/Kconfig.name b/src/mainboard/hp/pavilion_g7_2247us/Kconfig.name
new file mode 100644
index 0000000..dffe2ad
--- /dev/null
+++ b/src/mainboard/hp/pavilion_g7_2247us/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_HP_PAVILION_G7_2247US
+ bool "HP Pavilion g7-2247us Notebook PC"
diff --git a/src/mainboard/hp/pavilion_g7_2247us/Makefile.inc b/src/mainboard/hp/pavilion_g7_2247us/Makefile.inc
new file mode 100644
index 0000000..cd5b014
--- /dev/null
+++ b/src/mainboard/hp/pavilion_g7_2247us/Makefile.inc
@@ -0,0 +1,4 @@
+ramstage-y += ec.c
+romstage-y += early_southbridge.c
+romstage-y += gpio.c
+ramstage-y += gnvs.c
diff --git a/src/mainboard/hp/pavilion_g7_2247us/acpi/ec.asl b/src/mainboard/hp/pavilion_g7_2247us/acpi/ec.asl
new file mode 100644
index 0000000..f9ebc75
--- /dev/null
+++ b/src/mainboard/hp/pavilion_g7_2247us/acpi/ec.asl
@@ -0,0 +1,2 @@
+#include "../ec.h"
+#include <ec/quanta/ene_kb3940q/acpi/ec.asl>
diff --git a/src/mainboard/hp/pavilion_g7_2247us/acpi/mainboard.asl b/src/mainboard/hp/pavilion_g7_2247us/acpi/mainboard.asl
new file mode 100644
index 0000000..8ecc128
--- /dev/null
+++ b/src/mainboard/hp/pavilion_g7_2247us/acpi/mainboard.asl
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <mainboard/google/butterfly/onboard.h>
+
+Scope (\_SB) {
+ Device (LID0)
+ {
+ Name (_HID, EisaId("PNP0C0D"))
+ Method (_LID, 0)
+ {
+ Store (\_SB.PCI0.LPCB.EC0.LIDF, \LIDS)
+ Return (\LIDS)
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, EisaId("PNP0C0C"))
+ }
+
+ Device (TPAD)
+ {
+ Name (_ADR, 0x0)
+ Name (_UID, 1)
+
+ // Report as a Sleep Button device so Linux will
+ // automatically enable it as a wake source
+ Name(_HID, EisaId("PNP0C0E"))
+
+ // Trackpad Wake is GPIO11, wake from S3
+ Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 })
+
+ Name(_CRS, ResourceTemplate()
+ {
+ // PIRQG -> GSI22
+ Interrupt (ResourceConsumer, EDGE, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+
+ // SMBUS Address 0x67
+ VendorShort (ADDR) { BOARD_TRACKPAD_I2C_ADDR }
+ })
+ }
+
+}
+
+// Battery information
+Name (BATV, "GOOGLE")
diff --git a/src/mainboard/hp/pavilion_g7_2247us/acpi/platform.asl b/src/mainboard/hp/pavilion_g7_2247us/acpi/platform.asl
new file mode 100644
index 0000000..c2862c9
--- /dev/null
+++ b/src/mainboard/hp/pavilion_g7_2247us/acpi/platform.asl
@@ -0,0 +1,10 @@
+Method(_WAK,1)
+{
+ /* FIXME: EC support */
+ Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/hp/pavilion_g7_2247us/acpi/superio.asl b/src/mainboard/hp/pavilion_g7_2247us/acpi/superio.asl
new file mode 100644
index 0000000..f2b35ba
--- /dev/null
+++ b/src/mainboard/hp/pavilion_g7_2247us/acpi/superio.asl
@@ -0,0 +1 @@
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/hp/pavilion_g7_2247us/acpi_tables.c b/src/mainboard/hp/pavilion_g7_2247us/acpi_tables.c
new file mode 100644
index 0000000..2997587
--- /dev/null
+++ b/src/mainboard/hp/pavilion_g7_2247us/acpi_tables.c
@@ -0,0 +1 @@
+/* dummy */
diff --git a/src/mainboard/hp/pavilion_g7_2247us/board_info.txt b/src/mainboard/hp/pavilion_g7_2247us/board_info.txt
new file mode 100644
index 0000000..cdbf8b8
--- /dev/null
+++ b/src/mainboard/hp/pavilion_g7_2247us/board_info.txt
@@ -0,0 +1,4 @@
+Category: laptop
+ROM protocol: SPI
+Flashrom support: n
+FIXME: put ROM package, ROM socketed, Release year
diff --git a/src/mainboard/hp/pavilion_g7_2247us/devicetree.cb b/src/mainboard/hp/pavilion_g7_2247us/devicetree.cb
new file mode 100644
index 0000000..018f18d
--- /dev/null
+++ b/src/mainboard/hp/pavilion_g7_2247us/devicetree.cb
@@ -0,0 +1,123 @@
+chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+ register "gfx.link_frequency_270_mhz" = "1"
+ register "gfx.ndid" = "3"
+ register "gfx.use_spread_spectrum_clock" = "1"
+ register "gpu_cpu_backlight" = "0x00001312"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2000"
+ register "gpu_panel_power_backlight_on_delay" = "2000"
+ register "gpu_panel_power_cycle_delay" = "5"
+ register "gpu_panel_power_down_delay" = "500"
+ register "gpu_panel_power_up_delay" = "600"
+ register "gpu_pch_backlight" = "0x13121312"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0x0 on
+ end
+ end
+ chip cpu/intel/model_206ax # FIXME: check all registers
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0xacac off
+ end
+ end
+ end
+ device domain 0x0 on
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x000c0069"
+ register "gen2_dec" = "0x000c0381"
+ register "gen3_dec" = "0x00000000"
+ register "gen4_dec" = "0x00000000"
+ register "gpi13_routing" = "2"
+ register "p_cnt_throttling_supported" = "1"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x1"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+ device pci 14.0 on # USB 3.0 Controller
+ subsystemid 0x103c 0x1843
+ end
+ device pci 16.0 on # Management Engine Interface 1
+ subsystemid 0x103c 0x1843
+ end
+ device pci 16.1 off # Management Engine Interface 2
+ end
+ device pci 16.2 off # Management Engine IDE-R
+ end
+ device pci 16.3 off # Management Engine KT
+ end
+ device pci 19.0 off # Intel Gigabit Ethernet
+ end
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x103c 0x1843
+ end
+ device pci 1b.0 on # High Definition Audio Audio controller
+ subsystemid 0x103c 0x1843
+ end
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x103c 0x1843
+ end
+ device pci 1c.1 on # PCIe Port #2
+ subsystemid 0x103c 0x1843
+ end
+ device pci 1c.2 on # PCIe Port #3
+ subsystemid 0x103c 0x1843
+ end
+ device pci 1c.3 off # PCIe Port #4
+ end
+ device pci 1c.4 off # PCIe Port #5
+ end
+ device pci 1c.5 off # PCIe Port #6
+ end
+ device pci 1c.6 off # PCIe Port #7
+ end
+ device pci 1c.7 off # PCIe Port #8
+ end
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x103c 0x1843
+ end
+ device pci 1e.0 off # PCI bridge
+ end
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ chip ec/quanta/ene_kb3940q
+ # 60/64 KBC
+ device pnp ff.1 on
+ end
+ end
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x103c 0x1843
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x103c 0x1843
+ end
+ device pci 1f.5 off # SATA Controller 2
+ end
+ device pci 1f.6 off # Thermal
+ end
+ end
+ device pci 00.0 on # Host bridge Host bridge
+ subsystemid 0x103c 0x1843
+ end
+ device pci 01.0 off # PCIe Bridge for discrete graphics
+ end
+ device pci 02.0 on # Internal graphics VGA controller
+ subsystemid 0x103c 0x1843
+ end
+ end
+end
diff --git a/src/mainboard/hp/pavilion_g7_2247us/dsdt.asl b/src/mainboard/hp/pavilion_g7_2247us/dsdt.asl
new file mode 100644
index 0000000..5e95108
--- /dev/null
+++ b/src/mainboard/hp/pavilion_g7_2247us/dsdt.asl
@@ -0,0 +1,30 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x03, // DSDT revision: ACPI v3.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20141018 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+ #include "acpi/mainboard.asl"
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+ #include <southbridge/intel/bd82x6x/acpi/platform.asl>
+ /* global NVS and variables. */
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+ }
+}
diff --git a/src/mainboard/hp/pavilion_g7_2247us/early_southbridge.c b/src/mainboard/hp/pavilion_g7_2247us/early_southbridge.c
new file mode 100644
index 0000000..69cbe70
--- /dev/null
+++ b/src/mainboard/hp/pavilion_g7_2247us/early_southbridge.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <arch/acpi.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit_native.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include <southbridge/intel/common/gpio.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+
+void pch_enable_lpc(void)
+{
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f00);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0069);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0381);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+}
+
+void rcba_config(void)
+{
+ /* Disable devices. */
+ RCBA32(0x3414) = 0x00000020;
+ RCBA32(0x3418) = 0x17f81fe3;
+
+}
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, 0 },
+ { 1, 0, 0 },
+ { 0, 0, 1 },
+ { 0, 0, 1 },
+ { 1, 1, 2 },
+ { 0, 0, 2 },
+ { 0, 0, 3 },
+ { 0, 0, 3 },
+ { 0, 0, 4 },
+ { 1, 1, 4 },
+ { 1, 1, 5 },
+ { 0, 0, 5 },
+ { 0, 0, 6 },
+ { 0, 0, 6 },
+};
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+}
+
+/* FIXME: Put proper SPD map here. */
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[1], 0x51, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+ read_spd(&spd[3], 0x53, id_only);
+}
diff --git a/src/mainboard/hp/pavilion_g7_2247us/ec.c b/src/mainboard/hp/pavilion_g7_2247us/ec.c
new file mode 100644
index 0000000..cca12bd
--- /dev/null
+++ b/src/mainboard/hp/pavilion_g7_2247us/ec.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <ec/quanta/ene_kb3940q/ec.h>
+#include "ec.h"
+
+void butterfly_ec_init(void)
+{
+ printk(BIOS_DEBUG, "Butterfly EC Init\n");
+
+ /* Report EC info */
+ /* EC version: 6 bytes */
+ printk(BIOS_DEBUG, " EC version: %c%c%c%c%c%c\n",
+ ec_mem_read(EC_FW_VER0), ec_mem_read(EC_FW_VER1),
+ ec_mem_read(EC_FW_VER2), ec_mem_read(EC_FW_VER3),
+ ec_mem_read(EC_FW_VER4), ec_mem_read(EC_FW_VER5));
+
+ /* Disable wake on USB, LAN & RTC */
+ /* Enable Wake from Keyboard */
+ ec_mem_write(EC_EC_PSW, EC_PSW_IKB);
+
+}
diff --git a/src/mainboard/hp/pavilion_g7_2247us/ec.h b/src/mainboard/hp/pavilion_g7_2247us/ec.h
new file mode 100644
index 0000000..6cb0748
--- /dev/null
+++ b/src/mainboard/hp/pavilion_g7_2247us/ec.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef BUTTERFLY_EC_H
+#define BUTTERFLY_EC_H
+
+#define EC_SCI_GPI 13 /* GPIO13 is EC_SCI# */
+
+/* EC SMI sources TODO: MLR- make defines */
+
+#ifndef __ACPI__
+extern void butterfly_ec_init(void);
+#endif
+
+#endif // BUTTERFLY_EC_H
diff --git a/src/mainboard/hp/pavilion_g7_2247us/gnvs.c b/src/mainboard/hp/pavilion_g7_2247us/gnvs.c
new file mode 100644
index 0000000..6b731cc
--- /dev/null
+++ b/src/mainboard/hp/pavilion_g7_2247us/gnvs.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/hp/pavilion_g7_2247us/gpio.c b/src/mainboard/hp/pavilion_g7_2247us/gpio.c
new file mode 100644
index 0000000..2ff8f9e
--- /dev/null
+++ b/src/mainboard/hp/pavilion_g7_2247us/gpio.c
@@ -0,0 +1,242 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_GPIO,
+ .gpio26 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio9 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_OUTPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio23 = GPIO_DIR_OUTPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio25 = GPIO_DIR_INPUT,
+ .gpio26 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio21 = GPIO_LEVEL_LOW,
+ .gpio23 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio24 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio11 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_GPIO,
+ .gpio41 = GPIO_MODE_GPIO,
+ .gpio42 = GPIO_MODE_GPIO,
+ .gpio43 = GPIO_MODE_GPIO,
+ .gpio44 = GPIO_MODE_GPIO,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_GPIO,
+ .gpio59 = GPIO_MODE_GPIO,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_GPIO,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio40 = GPIO_DIR_INPUT,
+ .gpio41 = GPIO_DIR_INPUT,
+ .gpio42 = GPIO_DIR_INPUT,
+ .gpio43 = GPIO_DIR_INPUT,
+ .gpio44 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_INPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio58 = GPIO_DIR_INPUT,
+ .gpio59 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+ .gpio61 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio49 = GPIO_LEVEL_LOW,
+ .gpio53 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_HIGH,
+ .gpio61 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_GPIO,
+ .gpio65 = GPIO_MODE_GPIO,
+ .gpio66 = GPIO_MODE_GPIO,
+ .gpio67 = GPIO_MODE_GPIO,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_OUTPUT,
+ .gpio65 = GPIO_DIR_OUTPUT,
+ .gpio66 = GPIO_DIR_OUTPUT,
+ .gpio67 = GPIO_DIR_OUTPUT,
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_INPUT,
+ .gpio75 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio64 = GPIO_LEVEL_LOW,
+ .gpio65 = GPIO_LEVEL_LOW,
+ .gpio66 = GPIO_LEVEL_LOW,
+ .gpio67 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/hp/pavilion_g7_2247us/hda_verb.c b/src/mainboard/hp/pavilion_g7_2247us/hda_verb.c
new file mode 100644
index 0000000..b71d62d
--- /dev/null
+++ b/src/mainboard/hp/pavilion_g7_2247us/hda_verb.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76d9, /* Codec Vendor / Device ID: IDT */
+ 0x103c1843, /* Subsystem ID */
+
+ 0x00000007, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x0, 0x103c1843),
+
+ /* NID 0x0a. */
+ AZALIA_PIN_CFG(0x0, 0x0a, 0x40f000f0),
+
+ /* NID 0x0b. */
+ AZALIA_PIN_CFG(0x0, 0x0b, 0x0421101f),
+
+ /* NID 0x0c. */
+ AZALIA_PIN_CFG(0x0, 0x0c, 0x04a11020),
+
+ /* NID 0x0d. */
+ AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110),
+
+ /* NID 0x0f. */
+ AZALIA_PIN_CFG(0x0, 0x0f, 0x40f000f0),
+
+ /* NID 0x11. */
+ AZALIA_PIN_CFG(0x0, 0x11, 0xd5a30130),
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+
+ 0x00000004, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x3, 0x80860101),
+
+ /* NID 0x05. */
+ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
+
+ /* NID 0x06. */
+ AZALIA_PIN_CFG(0x3, 0x06, 0x58560020),
+
+ /* NID 0x07. */
+ AZALIA_PIN_CFG(0x3, 0x07, 0x58560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/hp/pavilion_g7_2247us/mainboard.c b/src/mainboard/hp/pavilion_g7_2247us/mainboard.c
new file mode 100644
index 0000000..25c7183
--- /dev/null
+++ b/src/mainboard/hp/pavilion_g7_2247us/mainboard.c
@@ -0,0 +1,28 @@
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/quanta/ene_kb3940q/ec.h>
+#include "ec.h"
+#include <console/console.h>
+#include <pc80/keyboard.h>
+
+static void mainboard_init(device_t dev)
+{
+ butterfly_ec_init();
+ ec_mem_write(EC_KBID_REG, EC_KBD_EN);
+ pc_keyboard_init(NO_AUX_DEVICE);
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+
+ /* FIXME: fix those values*/
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/hp/pavilion_g7_2247us/romstage.c b/src/mainboard/hp/pavilion_g7_2247us/romstage.c
new file mode 100644
index 0000000..f1839f0
--- /dev/null
+++ b/src/mainboard/hp/pavilion_g7_2247us/romstage.c
@@ -0,0 +1 @@
+/* dummy file */
--
To view, visit https://review.coreboot.org/23352
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6f91595b0c06d683afb74eb54b3b78bd0458d6a1
Gerrit-Change-Number: 23352
Gerrit-PatchSet: 1
Gerrit-Owner: Marty E. Plummer <hanetzer at startmail.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180122/4e07f004/attachment-0001.html>
More information about the coreboot-gerrit
mailing list