[coreboot-gerrit] Change in coreboot[master]: mainboard/google/zoombini/variants/meowth: configure FP MCU SPI device

[Vincent Palatin (Code Review)]

Vincent Palatin has uploaded this change for review. ( https://review.coreboot.org/23328


Change subject: mainboard/google/zoombini/variants/meowth: configure FP MCU SPI device
......................................................................

mainboard/google/zoombini/variants/meowth: configure FP MCU SPI device

Configure the FP MCU interface on GSPI1.

Signed-off-by: Vincent Palatin <vpalatin at chromium.org>

BRANCH=none
BUG=b:71986991
TEST=boot on reworked Meowth with a ZerbleBarn board attached to
GSPI1 and see the cros_ec kernel driver detecting it.

Change-Id: Ib874ddaf4948a766fd05c11f4675dbfdb679059d
---
M src/mainboard/google/zoombini/Kconfig
M src/mainboard/google/zoombini/variants/meowth/devicetree.cb
2 files changed, 10 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/23328/1

diff --git a/src/mainboard/google/zoombini/Kconfig b/src/mainboard/google/zoombini/Kconfig
index f09abfc..813745c 100644
--- a/src/mainboard/google/zoombini/Kconfig
+++ b/src/mainboard/google/zoombini/Kconfig
@@ -3,6 +3,7 @@
 	def_bool n
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_I2C_GENERIC
+	select DRIVERS_SPI_ACPI
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_LPC
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
index b2c1f06..2317c90 100644
--- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
+++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
@@ -98,7 +98,15 @@
 		device pci 1e.0 on  end # UART #0
 		device pci 1e.1 off end # UART #1
 		device pci 1e.2 on  end # GSPI #0
-		device pci 1e.3 on  end # GSPI #1
+		device pci 1e.3 on
+			chip drivers/spi/acpi
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A22_IRQ)"
+				device spi 0 on end
+			end
+		end # GSPI #1
 		device pci 1f.0 on
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end

-- 
To view, visit https://review.coreboot.org/23328
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib874ddaf4948a766fd05c11f4675dbfdb679059d
Gerrit-Change-Number: 23328
Gerrit-PatchSet: 1
Gerrit-Owner: Vincent Palatin <vpalatin at chromium.org>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180119/599577e5/attachment-0001.html>