[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Port SD Controller W/A from Intel Reference code

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/23313


Change subject: soc/intel/cannonlake: Port SD Controller W/A from Intel Reference code
......................................................................

soc/intel/cannonlake: Port SD Controller W/A from Intel Reference code

Solution: To do an additional config read to the SD controller
after the controller has been power gated (put to D3)

Change-Id: Ia2438c767332b0e2d413c71b06b052bf9ab4a96c
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/cannonlake/acpi/scs.asl
1 file changed, 13 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/23313/1

diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl
index b84bedd..27f082c 100644
--- a/src/soc/intel/cannonlake/acpi/scs.asl
+++ b/src/soc/intel/cannonlake/acpi/scs.asl
@@ -51,23 +51,34 @@
 	Device (SDXC)
 	{
 		Name (_ADR, 0x00140005)
+		Name (TEMP, 0)
 
 		OperationRegion (SDPC, PCI_Config, 0x00, 0x100)
 		Field (SDPC, WordAcc, NoLock, Preserve)
 		{
-			Offset(0xA2),  /* Device Power Gate config */
+			Offset (0x84),	/* PMECTRLSTATUS */
+			PMCR, 16,
+			Offset (0xa2),	/* PG_CONFIG */
 			, 2,
-			PGEN, 1 /* PGE - PG Enable */
+			PGEN, 1,	/* PG_ENABLE */
 		}
 
 		Method (_PS0, 0, Serialized)
 		{
 			Store (0, PGEN) /* Disable PG */
+
+			/* Set Power State to D0 */
+			And (PMCR, 0xFFFC, PMCR)
+			Store (PMCR, ^TEMP)
 		}
 
 		Method (_PS3, 0, Serialized)
 		{
 			Store (1, PGEN) /* Enable PG */
+
+			/* Set Power State to D3 */
+			Or (PMCR, 0x0003, PMCR)
+			Store (PMCR, ^TEMP)
 		}
 	} /* Device (SDXC) */
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia2438c767332b0e2d413c71b06b052bf9ab4a96c
Gerrit-Change-Number: 23313
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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