[coreboot-gerrit] Change in coreboot[master]: zoombini: meowth: add ACPI entry for cr50 TPM

[Caveh Jalali (Code Review)]

Caveh Jalali has uploaded this change for review. ( https://review.coreboot.org/23310


Change subject: zoombini: meowth: add ACPI entry for cr50 TPM
......................................................................

zoombini: meowth: add ACPI entry for cr50 TPM

this adds coreboot device tree entries on zoombini & meowth for the
cr50 TPM.  this is based on what we do for fizz.

BUG=b:71722449
TEST=booted to linux on meowth: tpm_version command now sees TPM.

localhost ~ # tpm_version
  TPM 2.0 Version Info:
  Chip Version:        2.0.0.0
  Spec Family:         322e3000
  Spec Family String:  2.0
  Spec Level:          0
  Spec Revision:       116
  Manufacturer Info:   43524f53
  Manufacturer String: CROS
  Vendor ID:           xCG fTPM
  TPM Model:           00000001
  Firmware Version:    0ad551830bcf7a82
localhost ~ # uname -a
Linux localhost 4.14.13 #3 SMP PREEMPT Sat Jan 13 02:55:45 PST 2018 x86_64 Genuine Intel(R) CPU 0000 @ 1.00GHz GenuineIntel GNU/Linux
localhost ~ #

Change-Id: I9d503334502503ef49515e4a8736d967bc454a98
Signed-off-by: Caveh Jalali <caveh at google.com>
---
M src/mainboard/google/zoombini/Kconfig
M src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
M src/mainboard/google/zoombini/variants/meowth/devicetree.cb
3 files changed, 17 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/23310/1

diff --git a/src/mainboard/google/zoombini/Kconfig b/src/mainboard/google/zoombini/Kconfig
index 4214dd6..64180f3 100644
--- a/src/mainboard/google/zoombini/Kconfig
+++ b/src/mainboard/google/zoombini/Kconfig
@@ -3,6 +3,7 @@
 	def_bool n
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_I2C_GENERIC
+	select DRIVERS_SPI_ACPI
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_LPC
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
index da40baf..44ea0bb 100644
--- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
@@ -91,7 +91,14 @@
 		device pci 1d.7 off end # PCI Express Port 16
 		device pci 1e.0 on  end # UART #0
 		device pci 1e.1 off end # UART #1
-		device pci 1e.2 on  end # GSPI #0
+		device pci 1e.2 on
+			chip drivers/spi/acpi
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "compat_string" = ""google,cr50""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C12_IRQ)"
+				device spi 0 on end
+			end
+		end # GSPI #0
 		device pci 1e.3 on  end # GSPI #1
 		device pci 1f.0 on
 			chip ec/google/chromeec
diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
index b2c1f06..f0fd894 100644
--- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
+++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
@@ -97,7 +97,14 @@
 		device pci 1d.7 off end # PCI Express Port 16
 		device pci 1e.0 on  end # UART #0
 		device pci 1e.1 off end # UART #1
-		device pci 1e.2 on  end # GSPI #0
+		device pci 1e.2 on
+			chip drivers/spi/acpi
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "compat_string" = ""google,cr50""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C12_IRQ)"
+				device spi 0 on end
+			end
+		end # GSPI #0
 		device pci 1e.3 on  end # GSPI #1
 		device pci 1f.0 on
 			chip ec/google/chromeec

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9d503334502503ef49515e4a8736d967bc454a98
Gerrit-Change-Number: 23310
Gerrit-PatchSet: 1
Gerrit-Owner: Caveh Jalali <caveh at google.com>
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