[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge/include/soc/southbridge.h: Replace SATA magic numbers

[Richard Spiegel (Code Review)]

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/23296


Change subject: amd/stoneyridge/include/soc/southbridge.h: Replace SATA magic numbers
......................................................................

amd/stoneyridge/include/soc/southbridge.h: Replace SATA magic numbers

CONFIG_STONEYRIDGE_SATA_MODE is compared against "magical numbers".
Because actual literals are in AGESA.h and adding agesa_headers.h to
southbridge.h causes compile errors, move comparison code from southbridge.h
to southbridge.c (where they are actually used). Replace these numbers
with actual literals.

BUG=b:71754828
TEST=Build kahlee.

Change-Id: I711473bf492d5ceca026ccd112c2c389a23bdbf9
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/southbridge.c
2 files changed, 14 insertions(+), 14 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/23296/1

diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index d9016bc..4ec8ac7 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -294,20 +294,6 @@
 #define WIDEIO_RANGE_ERROR		-1
 #define TOTAL_WIDEIO_PORTS		3
 
-static inline int sb_sata_enable(void)
-{
-	/* True if IDE or AHCI. */
-	return (CONFIG_STONEYRIDGE_SATA_MODE == 0) ||
-					(CONFIG_STONEYRIDGE_SATA_MODE == 2);
-}
-
-static inline int sb_ide_enable(void)
-{
-	/* True if IDE or LEGACY IDE. */
-	return (CONFIG_STONEYRIDGE_SATA_MODE == 0) ||
-					(CONFIG_STONEYRIDGE_SATA_MODE == 3);
-}
-
 void sb_enable_rom(void);
 void configure_stoneyridge_uart(void);
 void sb_clk_output_48Mhz(void);
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 0f92001..9b368e6 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -39,6 +39,20 @@
 			|| (CONFIG_STONEYRIDGE_SATA_MODE == SataLegacyIde));
 }
 
+static inline int sb_sata_enable(void)
+{
+	/* True if IDE or AHCI. */
+	return (CONFIG_STONEYRIDGE_SATA_MODE == SataNativeIde) ||
+		(CONFIG_STONEYRIDGE_SATA_MODE == SataAhci);
+}
+
+static inline int sb_ide_enable(void)
+{
+	/* True if IDE or LEGACY IDE. */
+	return (CONFIG_STONEYRIDGE_SATA_MODE == SataNativeIde) ||
+		(CONFIG_STONEYRIDGE_SATA_MODE == SataLegacyIde);
+}
+
 void SetFchResetParams(FCH_RESET_INTERFACE *params)
 {
 	params->Xhci0Enable = IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE);

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I711473bf492d5ceca026ccd112c2c389a23bdbf9
Gerrit-Change-Number: 23296
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
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