[coreboot-gerrit] Change in coreboot[master]: [WIP]sb/intel/i82801ix: Use common RCBA code
Arthur Heymans (Code Review)
gerrit at coreboot.org
Tue Jan 16 15:20:57 CET 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23288
Change subject: [WIP]sb/intel/i82801ix: Use common RCBA code
......................................................................
[WIP]sb/intel/i82801ix: Use common RCBA code
Tested, still boots on Thinkpad X200.
Change-Id: I56a1dbf9c364f040ffb110121b6a28494ddb8f90
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/lenovo/x200/romstage.c
M src/northbridge/intel/gm45/gm45.h
M src/northbridge/intel/gm45/pcie.c
M src/southbridge/intel/common/rcba.h
M src/southbridge/intel/i82801ix/dmi_setup.c
M src/southbridge/intel/i82801ix/early_init.c
M src/southbridge/intel/i82801ix/i82801ix.c
M src/southbridge/intel/i82801ix/i82801ix.h
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801ix/smihandler.c
10 files changed, 57 insertions(+), 66 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/23288/1
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index d8ed039..9db4133 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -30,6 +30,7 @@
#include <romstage_handoff.h>
#include <console/console.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
+#include <southbridge/intel/common/rcba.h>
#include <northbridge/intel/gm45/gm45.h>
#include "gpio.h"
#include <timestamp.h>
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 34f734c..a43da16 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -17,6 +17,7 @@
#ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__
#define __NORTHBRIDGE_INTEL_GM45_GM45_H__
+#include <southbridge/intel/common/rcba.h>
#include "southbridge/intel/i82801ix/i82801ix.h"
#ifndef __ACPI__
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c
index 47203b4..c42e707 100644
--- a/src/northbridge/intel/gm45/pcie.c
+++ b/src/northbridge/intel/gm45/pcie.c
@@ -21,6 +21,7 @@
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <console/console.h>
+#include <southbridge/intel/common/rcba.h>
#include "gm45.h"
diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h
index 1399fde..d078e80 100644
--- a/src/southbridge/intel/common/rcba.h
+++ b/src/southbridge/intel/common/rcba.h
@@ -58,6 +58,8 @@
#define V1CTL 0x0020 /* 32bit */
#define V1STS 0x0026 /* 16bit */
+#define PAT 0x0030
+
#define RCTCL 0x0100 /* 32bit */
#define ESD 0x0104 /* 32bit */
#define ULD 0x0110 /* 32bit */
@@ -77,6 +79,11 @@
#define RP5BA 0x0178 /* 64bit */
#define RP6D 0x0180 /* 32bit */
#define RP6BA 0x0188 /* 64bit */
+#define LCAP 0x01a4
+#define LCTL 0x01a8
+#define LSTS 0x01aa
+#define DMIC 0x0234
+#define RPFN_ICH 0x0238
#define RPC 0x0400 /* 32bit */
#define RPFN 0x0404 /* 32bit */
@@ -99,6 +106,8 @@
#define IOTR2 0x1e90 /* 64bit */
#define IOTR3 0x1e98 /* 64bit */
+#define DMC 0x2010
+
#define TCTL 0x3000 /* 8bit */
@@ -159,9 +168,11 @@
#define BUC 0x3414 /* 32bit */
#define PCH_DISABLE_GBE (1 << 5)
#define FD 0x3418 /* 32bit */
+#define FDSW 0x3420
#define DISPBDF 0x3424 /* 16bit */
#define FD2 0x3428 /* 32bit */
#define CG 0x341c /* 32bit */
+#define MAP 0x35f0
/* Function Disable 1 RCBA 0x3418 */
#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))
diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c
index e47586b..4d02096 100644
--- a/src/southbridge/intel/i82801ix/dmi_setup.c
+++ b/src/southbridge/intel/i82801ix/dmi_setup.c
@@ -18,6 +18,7 @@
#include <device/pci_def.h>
#include <console/console.h>
#include <northbridge/intel/gm45/gm45.h>
+#include <southbridge/intel/common/rcba.h>
#include "i82801ix.h"
/* VC1 Port Arbitration Table */
@@ -44,7 +45,7 @@
int i;
u32 reg32;
- RCBA32(RCBA_V1CAP) = (RCBA32(RCBA_V1CAP) & ~(0x7f<<16)) | (0x12<<16);
+ RCBA32(V1CAP) = (RCBA32(V1CAP) & ~(0x7f<<16)) | (0x12<<16);
RCBA32(0x0088) = 0x00109000;
RCBA16(0x01fc) = 0x060b;
@@ -56,55 +57,55 @@
/* VC1 setup for isochronous transfers: */
/* Set VC1 virtual channel id to 1. */
- RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7 << 24)) | (0x1 << 24);
+ RCBA32(V1CTL) = (RCBA32(V1CTL) & ~(0x7 << 24)) | (0x1 << 24);
/* Enable TC7 traffic on VC1. */
- RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7f << 1)) | (1 << 7);
+ RCBA32(V1CTL) = (RCBA32(V1CTL) & ~(0x7f << 1)) | (1 << 7);
/* Disable TC7-TC1 traffic on VC0. */
- RCBA32(RCBA_V0CTL) &= ~(0x7f << 1);
+ RCBA32(V0CTL) &= ~(0x7f << 1);
/* TC7-TC1 traffic on PCIe root ports will be disabled in pci driver. */
/* Set table type to time-based WRR. */
- RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7 << 17)) | (0x4 << 17);
+ RCBA32(V1CTL) = (RCBA32(V1CTL) & ~(0x7 << 17)) | (0x4 << 17);
/* Program port arbitration table. */
for (i = 0; i < sizeof(vc1_pat); ++i)
- RCBA8(RCBA_PAT + i) = vc1_pat[i];
+ RCBA8(PAT + i) = vc1_pat[i];
/* Load port arbitration table. */
- RCBA32(RCBA_V1CTL) |= (1 << 16);
+ RCBA32(V1CTL) |= (1 << 16);
/* Enable VC1. */
- RCBA32(RCBA_V1CTL) |= (1 << 31);
+ RCBA32(V1CTL) |= (1 << 31);
/* Setup RCRB: */
/* Set component id to 2 for southbridge, northbridge has id 1. */
- RCBA8(RCBA_ESD + 2) = 2;
+ RCBA8(ESD + 2) = 2;
/* Set target port number and target component id of the northbridge. */
- RCBA8(RCBA_ULD + 3) = 1;
- RCBA8(RCBA_ULD + 2) = 1;
+ RCBA8(ULD + 3) = 1;
+ RCBA8(ULD + 2) = 1;
/* Set target rcrb base address, i.e. DMIBAR. */
- RCBA32(RCBA_ULBA) = (uintptr_t)DEFAULT_DMIBAR;
+ RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR;
/* Enable ASPM. */
if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) {
- reg32 = RCBA32(RCBA_DMC);
+ reg32 = RCBA32(DMC);
/* Enable mobile specific power saving (set this first). */
reg32 = (reg32 & ~(3 << 10)) | (1 << 10);
- RCBA32(RCBA_DMC) = reg32;
+ RCBA32(DMC) = reg32;
/* Enable DMI power savings. */
reg32 |= (1 << 19);
- RCBA32(RCBA_DMC) = reg32;
+ RCBA32(DMC) = reg32;
/* Advertise L0s and L1. */
- RCBA32(RCBA_LCAP) |= (3 << 10);
+ RCBA32(LCAP) |= (3 << 10);
/* Enable L0s and L1. */
- RCBA32(RCBA_LCTL) |= (3 << 0);
+ RCBA32(LCTL) |= (3 << 0);
} else {
/* Enable DMI power savings. */
- RCBA32(RCBA_DMC) |= (1 << 19);
+ RCBA32(DMC) |= (1 << 19);
/* Advertise L0s only. */
- RCBA32(RCBA_LCAP) = (RCBA32(RCBA_LCAP) & ~(3<<10)) | (1<<10);
+ RCBA32(LCAP) = (RCBA32(LCAP) & ~(3 << 10)) | (1 << 10);
/* Enable L0s only. */
- RCBA32(RCBA_LCTL) = (RCBA32(RCBA_LCTL) & ~(3<< 0)) | (1<< 0);
+ RCBA32(LCTL) = (RCBA32(LCTL) & ~(3 << 0)) | (1 << 0);
}
}
@@ -115,14 +116,15 @@
timeout = 0x7ffff;
printk(BIOS_DEBUG, "ICH9 waits for VC1 negotiation... ");
- while ((RCBA32(RCBA_V1STS) & (1 << 1)) && --timeout) {}
+ while ((RCBA32(V1STS) & (1 << 1)) && --timeout)
+ ;
if (!timeout)
printk(BIOS_DEBUG, "timeout!\n");
else
printk(BIOS_DEBUG, "done.\n");
/* Check for x2 DMI link. */
- if (((RCBA16(RCBA_LSTS) >> 4) & 0x3f) == 2) {
+ if (((RCBA16(LSTS) >> 4) & 0x3f) == 2) {
printk(BIOS_DEBUG, "x2 DMI link detected.\n");
RCBA32(0x2024) = (RCBA32(0x2024) & ~(7 << 21)) | (3 << 21);
RCBA16(0x20c4) |= (1 << 15);
@@ -133,7 +135,8 @@
timeout = 0x7ffff;
printk(BIOS_DEBUG, "ICH9 waits for port arbitration table update... ");
- while ((RCBA32(RCBA_V1STS) & (1 << 0)) && --timeout) {}
+ while ((RCBA32(V1STS) & (1 << 0)) && --timeout)
+ ;
if (!timeout)
printk(BIOS_DEBUG, "timeout!\n");
else
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c
index 7c4dafa..64fd790 100644
--- a/src/southbridge/intel/i82801ix/early_init.c
+++ b/src/southbridge/intel/i82801ix/early_init.c
@@ -17,6 +17,7 @@
#include <arch/io.h>
#include <timestamp.h>
#include <cpu/x86/tsc.h>
+#include <southbridge/intel/common/rcba.h>
#include "i82801ix.h"
uint64_t get_initial_timestamp(void)
diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c
index 7d44fba..4825981 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.c
+++ b/src/southbridge/intel/i82801ix/i82801ix.c
@@ -21,6 +21,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <console/console.h>
+#include <southbridge/intel/common/rcba.h>
#include "i82801ix.h"
typedef struct southbridge_intel_i82801ix_config config_t;
@@ -156,9 +157,9 @@
other constraints. */
if (i82801ix_function_disabled(PCI_DEVFN(0x19, 0)))
- RCBA32(RCBA_BUC) |= BUC_LAND;
+ RCBA32(BUC) |= BUC_LAND;
- reg32 = RCBA32(RCBA_FD);
+ reg32 = RCBA32(FD);
struct {
int devfn;
u32 mask;
@@ -188,20 +189,20 @@
if (i82801ix_function_disabled(functions[i].devfn))
reg32 |= functions[i].mask;
}
- RCBA32(RCBA_FD) = reg32;
- RCBA32(RCBA_FD) |= (1 << 0); /* BIOS must write this... */
- RCBA32(RCBA_FDSW) |= (1 << 7); /* Lock function-disable? */
+ RCBA32(FD) = reg32;
+ RCBA32(FD) |= (1 << 0); /* BIOS must write this... */
+ RCBA32(FDSW) |= (1 << 7); /* Lock function-disable? */
/* Hide PCIe root port PCI functions. RPFN is partially R/WO. */
- reg32 = RCBA32(RCBA_RPFN);
+ reg32 = RCBA32(RPFN_ICH);
for (i = 0; i < 6; ++i) {
if (i82801ix_function_disabled(PCI_DEVFN(0x1c, i)))
reg32 |= (1 << ((i * 4) + 3));
}
- RCBA32(RCBA_RPFN) = reg32;
+ RCBA32(RPFN_ICH) = reg32;
/* Lock R/WO UHCI controller #6 remapping. */
- RCBA32(RCBA_MAP) = RCBA32(RCBA_MAP);
+ RCBA32(MAP) = RCBA32(MAP);
}
static void i82801ix_init(void *chip_info)
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
index 38dfa38..a9230df 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.h
+++ b/src/southbridge/intel/i82801ix/i82801ix.h
@@ -25,11 +25,6 @@
#endif
#define DEFAULT_TBAR ((u8 *)0xfed1b000)
-#ifndef __ACPI__
-#define DEFAULT_RCBA ((u8 *)0xfed1c000)
-#else
-#define DEFAULT_RCBA 0xfed1c000
-#endif
#if IS_ENABLED(CONFIG_BOARD_EMULATION_QEMU_X86_Q35)
/*
@@ -154,31 +149,6 @@
#define SMB_SMI_EN (1 << 1)
#define HST_EN (1 << 0)
-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
-
-#define RCBA_V0CTL 0x0014
-#define RCBA_V1CAP 0x001c
-#define RCBA_V1CTL 0x0020
-#define RCBA_V1STS 0x0026
-#define RCBA_PAT 0x0030
-#define RCBA_ESD 0x0104
-#define RCBA_ULD 0x0110
-#define RCBA_ULBA 0x0118
-#define RCBA_LCAP 0x01a4
-#define RCBA_LCTL 0x01a8
-#define RCBA_LSTS 0x01aa
-#define RCBA_DMIC 0x0234
-#define RCBA_RPFN 0x0238
-#define RCBA_DMC 0x2010
-#define RCBA_HPTC 0x3404
-#define RCBA_BUC 0x3414
-#define RCBA_FD 0x3418 /* Function Disable, see below. */
-#define RCBA_CG 0x341c
-#define RCBA_FDSW 0x3420
-#define RCBA_MAP 0x35f0 /* UHCI controller #6 remapping */
-
#define BUC_LAND (1 << 5) /* LAN */
#define FD_SAD2 (1 << 25) /* SATA #2 */
#define FD_TTD (1 << 24) /* Thermal Throttle */
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index bc45b9d..dedcdd2 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -34,6 +34,7 @@
#include "nvs.h"
#include <southbridge/intel/common/pciehp.h>
#include <drivers/intel/gma/i915.h>
+#include <southbridge/intel/common/rcba.h>
#define NMI_OFF 0
@@ -332,10 +333,10 @@
u32 reg32;
/* Move HPET to default address 0xfed00000 and enable it */
- reg32 = RCBA32(RCBA_HPTC);
+ reg32 = RCBA32(HPTC);
reg32 |= (1 << 7); // HPET Address Enable
reg32 &= ~(3 << 0);
- RCBA32(RCBA_HPTC) = reg32;
+ RCBA32(HPTC) = reg32;
}
static void enable_clock_gating(void)
@@ -343,10 +344,10 @@
u32 reg32;
/* Enable DMI dynamic clock gating. */
- RCBA32(RCBA_DMIC) |= 3;
+ RCBA32(DMIC) |= 3;
/* Enable Clock Gating for most devices. */
- reg32 = RCBA32(RCBA_CG);
+ reg32 = RCBA32(CG);
reg32 |= (1 << 31); /* LPC dynamic clock gating */
/* USB UHCI dynamic clock gating: */
reg32 |= (1 << 29) | (1 << 28);
@@ -363,7 +364,7 @@
/* PCIe, DMI dynamic clock gating: */
reg32 |= (1 << 4) | (1 << 3) | (1 << 2) | (1 << 1);
reg32 |= (1 << 0); /* PCIe root port static clock gating */
- RCBA32(RCBA_CG) = reg32;
+ RCBA32(CG) = reg32;
/* Enable SPI dynamic clock gating. */
RCBA32(0x38c0) |= 7;
diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c
index 7ad00ed..73caa38 100644
--- a/src/southbridge/intel/i82801ix/smihandler.c
+++ b/src/southbridge/intel/i82801ix/smihandler.c
@@ -22,6 +22,7 @@
#include <cpu/x86/smm.h>
#include <device/pci_def.h>
#include <pc80/mc146818rtc.h>
+#include <southbridge/intel/common/rcba.h>
#include "i82801ix.h"
#include "nvs.h"
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I56a1dbf9c364f040ffb110121b6a28494ddb8f90
Gerrit-Change-Number: 23288
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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