[coreboot-gerrit] Change in coreboot[master]: intel/skylake: Add symbol SOC_IO_LPC_DECODE_ENABLE

[PraveenX Hodagatta Pranesh (Code Review)]

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/23264


Change subject: intel/skylake: Add symbol SOC_IO_LPC_DECODE_ENABLE
......................................................................

intel/skylake: Add symbol SOC_IO_LPC_DECODE_ENABLE

Both SKL and KBL shares same soc/intel/skylake code.
Enabling LPC IO Decode on KBL aslo causes UART slow
logging due to change in design.

The issue can be fixed by Introducing a new Kconfig
flag in skylake/Kconfig which is enabled in Saddle Brook
mainboard dir.

Change-Id: Ib07d6aaf5694eb0641b6ac2fa89720b6bb5ed8cf
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh at intel.com>
---
M src/mainboard/intel/saddlebrook/Kconfig
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/lpc.c
3 files changed, 12 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/23264/1

diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig
index df04286..a49804c 100644
--- a/src/mainboard/intel/saddlebrook/Kconfig
+++ b/src/mainboard/intel/saddlebrook/Kconfig
@@ -32,6 +32,7 @@
 	select SUPERIO_NUVOTON_NCT6776_COM_A
 	select SADDLEBROOK_USES_FSP1_1
 	select HAVE_CMOS_DEFAULT
+	select SOC_IO_LPC_DECODE_ENABLE
 
 
 config SADDLEBROOK_USES_FSP1_1
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 7bb16d2..ce972d0 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -355,4 +355,11 @@
 	hex
 	default 0xc35
 
+config SOC_IO_LPC_DECODE_ENABLE
+	bool
+	default n
+	help
+	  Choose this option to enable LPC IO Enable decoding on
+	  SaddleBrook Platform.
+
 endif
diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c
index 9cd450b..fa3282f 100644
--- a/src/soc/intel/skylake/lpc.c
+++ b/src/soc/intel/skylake/lpc.c
@@ -91,8 +91,10 @@
 	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
 
 	/* LPC IO Decode Enable */
-	lpc_en = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES);
-	pcr_write16(PID_DMI, PCR_DMI_LPCIOE, lpc_en);
+	if (IS_ENABLED(CONFIG_SOC_IO_LPC_DECODE_ENABLE)) {
+		lpc_en = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES);
+		pcr_write16(PID_DMI, PCR_DMI_LPCIOE, lpc_en);
+	}
 }
 
 static const struct reg_script pch_misc_init_script[] = {

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib07d6aaf5694eb0641b6ac2fa89720b6bb5ed8cf
Gerrit-Change-Number: 23264
Gerrit-PatchSet: 1
Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh at intel.com>
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