[coreboot-gerrit] Change in coreboot[master]: src/soc/intel/cannonlake: Update C-state latency control limits

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23220 )

Change subject: src/soc/intel/cannonlake: Update C-state latency control limits
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Patch Set 1: Verified+1

Build Successful 

https://qa.coreboot.org/job/coreboot-checkpatch/20314/ : SUCCESS

https://qa.coreboot.org/job/coreboot-gerrit/65622/ : SUCCESS


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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I0f5227f9c3c10c5a9e335ab118eb0ec185445374
Gerrit-Change-Number: 23220
Gerrit-PatchSet: 1
Gerrit-Owner: Vaibhav Shankar <vaibhav.shankar at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Shaunak Saha <shaunak.saha at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Thu, 11 Jan 2018 18:57:56 +0000
Gerrit-HasComments: No
Gerrit-HasLabels: Yes
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