[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: prev_sleep_state incorrect on G3 exit
Hannah Williams (Code Review)
gerrit at coreboot.org
Thu Jan 11 19:48:18 CET 2018
Hannah Williams has uploaded this change for review. ( https://review.coreboot.org/23221
Change subject: soc/intel/apollolake: prev_sleep_state incorrect on G3 exit
......................................................................
soc/intel/apollolake: prev_sleep_state incorrect on G3 exit
if waking up from S5, then prev_sleep_state was correct but not
from G3
Change-Id: I39011a0846f042d224a7cd65f736e749acc8ec75
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
M src/soc/intel/apollolake/pmutil.c
1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/23221/1
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index 162290a..251ff9c 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -186,6 +186,19 @@
ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
}
+/* Return 0, 3, or 5 to indicate the previous sleep state. */
+int soc_prev_sleep_state(const struct chipset_power_state *ps,
+ int prev_sleep_state)
+{
+ /* when WAK_STS is set, pm1_cnt will be used to decide the
+ * prev_sleep_state
+ */
+
+ if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon1 & COLD_BOOT_STS))
+ prev_sleep_state = ACPI_S5;
+ return prev_sleep_state;
+}
+
void enable_pm_timer_emulation(void)
{
/* ACPI PM timer emulation */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I39011a0846f042d224a7cd65f736e749acc8ec75
Gerrit-Change-Number: 23221
Gerrit-PatchSet: 1
Gerrit-Owner: Hannah Williams <hannah.williams at intel.com>
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