[coreboot-gerrit] Change in coreboot[master]: [WIP] mainboard/google/zoombini/variants/meowth: enable NVMe

[Bora Guvendik (Code Review)]

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/23208


Change subject: [WIP] mainboard/google/zoombini/variants/meowth: enable NVMe
......................................................................

[WIP] mainboard/google/zoombini/variants/meowth: enable NVMe

Turn on pcie ports 9,10. Enable Root Port 3 and setup clkreq 3

TEST: Not tested, need board.

Change-Id: I272b63b11e6b00ae5bdbef5a37ee517cc0636f6d
Signed-off-by: Bora Guvendik <bora.guvendik at intel.com>
---
M src/mainboard/google/zoombini/variants/meowth/devicetree.cb
1 file changed, 7 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/23208/1

diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
index 6372217..acc4b47 100644
--- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
+++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
@@ -51,6 +51,11 @@
 	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
 	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
 
+	# NVMe
+	register "PcieRpEnable[2]" = "1"	# Enable Root Port 3
+	register "PcieClkSrcUsage[3]" = "8"     # Clksrc 3 for PCIe Port 9
+	register "PcieClkSrcClkReq[3]" = "3"
+
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device
@@ -81,8 +86,8 @@
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 off end # PCI Express Port 9
-		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.0 on end # PCI Express Port 9
+		device pci 1d.1 on end # PCI Express Port 10
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off end # PCI Express Port 12
 		device pci 1d.4 off end # PCI Express Port 13

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I272b63b11e6b00ae5bdbef5a37ee517cc0636f6d
Gerrit-Change-Number: 23208
Gerrit-PatchSet: 1
Gerrit-Owner: Bora Guvendik <bora.guvendik at intel.com>
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