[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Reserve PMC IO resources

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/23202


Change subject: soc/intel/cannonlake: Reserve PMC IO resources
......................................................................

soc/intel/cannonlake: Reserve PMC IO resources

PMC controller gets hidden during FSP-Silicon initialization
using sideband interface on CNP-PCH. Hence unable to reserve
PMC IO resources during PCI enumeration process. This was causing
hang issue on non-chrome platform with CNP-PCH due to ABASE
corruption.

This patch ensures PMC IO resource (ABASE) is getting reserved
(IO address 0x1800-0x1900) and ACPI base is not overwritten by
other devices.

TEST=ABASE range is reserved along with LPC IO range during PCI
enumeration.

PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0
flags c0000100 index 20

Change-Id: I1fbc4339ae11058fb3daedf4ffedda1904fa52ec
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/cannonlake/lpc.c
1 file changed, 17 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/23202/1

diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index 23e7f6a..adeb949 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -204,3 +204,20 @@
 	i8259_configure_irq_trigger(9, 1);
 	clock_gate_8254(dev);
 }
+
+/* Fill up LPC IO resource structure inside SoC directory */
+void pch_lpc_soc_get_io_resources(void)
+{
+	/*
+	 * PMC pci device gets hidden from PCI bus due to Silicon
+	 * policy hence binding ACPI BASE aka ABASE (offset 0x20) with
+	 * LPC IO resources to ensure that ABASE falls under PCI reserved
+	 * IO memory range.
+	 *
+	 * Note: Don't add any more resource with same offset 0x20
+	 * under this device space.
+	 */
+	pch_lpc_add_new_resource(PCH_DEV_LPC, PCI_BASE_ADDRESS_4,
+			ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, IORESOURCE_IO |
+			IORESOURCE_ASSIGNED | IORESOURCE_FIXED);
+}

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1fbc4339ae11058fb3daedf4ffedda1904fa52ec
Gerrit-Change-Number: 23202
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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