[coreboot-gerrit] Change in coreboot[master]: mainboard/google/zoombini: add bootblock and ramstage init

[Nick Vaccaro (Code Review)]

Hello Nick Vaccaro,

I'd like you to do a code review. Please visit

    https://review.coreboot.org/23193

to review the following change.


Change subject: mainboard/google/zoombini: add bootblock and ramstage init
......................................................................

mainboard/google/zoombini: add bootblock and ramstage init

Add ramstage_ec_init() and bootblock_ec_init() routines.

BUG=b:69011806
BRANCH=chromeos-2016.05
TEST=none

Change-Id: Iba2d5237c7ce112db8ec26fe022bea0ca6b92ee2
Signed-off-by: Nick Vaccaro <nvaccaro at chromium.org>
---
M src/mainboard/google/zoombini/ec.c
1 file changed, 36 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/23193/1

diff --git a/src/mainboard/google/zoombini/ec.c b/src/mainboard/google/zoombini/ec.c
index d756444..18b0b04 100644
--- a/src/mainboard/google/zoombini/ec.c
+++ b/src/mainboard/google/zoombini/ec.c
@@ -14,10 +14,16 @@
  */
 
 #include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <ec/ec.h>
 #include <ec/google/chromeec/ec.h>
+#include <intelblocks/lpc_lib.h>
+#include <rules.h>
 #include <variant/ec.h>
 
-void mainboard_ec_init(void)
+static void ramstage_ec_init(void)
 {
 	const struct google_chromeec_event_info info = {
 		.log_events = MAINBOARD_EC_LOG_EVENTS,
@@ -26,5 +32,34 @@
 		.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
 	};
 
+	printk(BIOS_ERR, "mainboard: EC init\n");
+
 	google_chromeec_events_init(&info, acpi_is_wakeup_s3());
 }
+
+static void bootblock_ec_init(void)
+{
+	uint16_t ec_ioport_base;
+	size_t ec_ioport_size;
+
+	/*
+	* Set up LPC decoding for the ChromeEC I/O port ranges:
+	* - Ports 62/66, 60/64, and 200->208
+	* - ChromeEC specific communication I/O ports.
+	*/
+	lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64
+		| LPC_IOE_LGE_200);
+	google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
+	lpc_open_pmio_window(ec_ioport_base, ec_ioport_size);
+	write32((void *)0xfd882730, 0xfc0801);
+	write32((void *)0xfd882734, 0xfc0901);
+	printk(BIOS_ERR, "Lance DEBUG bootblock EC init\n");
+}
+
+void mainboard_ec_init(void)
+{
+	if (ENV_RAMSTAGE)
+		ramstage_ec_init();
+	else if (ENV_BOOTBLOCK)
+		bootblock_ec_init();
+}

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iba2d5237c7ce112db8ec26fe022bea0ca6b92ee2
Gerrit-Change-Number: 23193
Gerrit-PatchSet: 1
Gerrit-Owner: Nick Vaccaro <nvaccaro at google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro at chromium.org>
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